On 15 September 2014 09:17, Andreas Färber <afaer...@suse.de> wrote: > Am 15.09.2014 um 18:10 schrieb Peter Maydell: >> Our handling of exceptions and exception priorities for >> Cortex-M CPUs is totally wrong. We attempt to reuse the >> GIC priority handling code for interrupts, which then leaves >> the exceptions without the correct priority handling. Ideally >> we should rewrite this completely to give the M profile >> cores the architecturally mandated exception priority >> handling and masking, and stop trying to reuse the >> A/R profile core code at all. The two profiles are just >> too different for that to make sense. > > Are you saying we should dump the inheritence completely?
>From the GIC common class? Yes. You'd want the QOM CPU object to directly expose a bunch of input IRQ/GPIO lines for the various interrupt lines an M profile core has (and not the IRQ/FIQ lines we do now). Exception/interrupt handling and prioritization is much more closely coupled to the core in M profile so trying to model it as a separate device is part of our problems here. I should mention that this is all a bit academic as far as I'm personally concerned since M profile is not something I can spend much time on (better to think of it as "occasional fixes" mode rather than "mantained/supported"). If anybody wants to take on the rework I'm happy to review code but I'm unlikely to ever do it myself. -- PMM
