Hi Fabian,
11.06.2014 03:55, Fabian Aggeler wrote:
> Prepare for cp register banking by inserting every cp register twice,
> once for secure world and once for non-secure world.
>
> Signed-off-by: Fabian Aggeler <aggel...@ethz.ch>
> ---
> target-arm/cpu.h | 14 +++++++++++---
> target-arm/helper.c | 20 ++++++++++++++++----
> target-arm/translate.c | 19 +++++++++++++------
> 3 files changed, 40 insertions(+), 13 deletions(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 0b8042c..d4eab39 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -831,6 +831,7 @@ void armv7m_nvic_complete_irq(void *opaque, int irq);
> * Crn, Crm, opc1, opc2 fields
> * 32 or 64 bit register (ie is it accessed via MRC/MCR
> * or via MRRC/MCRR?)
> + * non-secure/secure bank (Aarch32 only)
> * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
> * (In this case crn and opc2 should be zero.)
> * For AArch64, there is no 32/64 bit size distinction;
> @@ -848,9 +849,16 @@ void armv7m_nvic_complete_irq(void *opaque, int irq);
> #define CP_REG_AA64_SHIFT 28
> #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
>
> -#define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2) \
> - (((cp) << 16) | ((is64) << 15) | ((crn) << 11) | \
> - ((crm) << 7) | ((opc1) << 3) | (opc2))
> +/* To enable banking of coprocessor registers depending on ns-bit we
> + * add a bit to distinguish between secure and non-secure cpregs in the
> + * hashtable.
> + */
> +#define CP_REG_NS_SHIFT 27
> +#define CP_REG_NS_MASK(nsbit) (nsbit << CP_REG_NS_SHIFT)
> +
> +#define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2, ns) \
> + (CP_REG_NS_MASK(ns) | ((cp) << 16) | ((is64) << 15) | \
> + ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
>
> #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
> (CP_REG_AA64_MASK | \
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index f9b2374..610245d 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2883,7 +2883,7 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Error
> **errp)
>
> static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
> void *opaque, int state,
> - int crm, int opc1, int opc2)
> + int crm, int opc1, int opc2, int nsbit)
> {
> /* Private utility function for define_one_arm_cp_reg_with_opaque():
> * add a single reginfo struct to the hash table.
> @@ -2917,7 +2917,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const
> ARMCPRegInfo *r,
> *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
> r2->opc0, opc1, opc2);
> } else {
> - *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
> + *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2, nsbit);
> }
> if (opaque) {
> r2->opaque = opaque;
> @@ -3066,8 +3066,20 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
> if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
> continue;
> }
> - add_cpreg_to_hashtable(cpu, r, opaque, state,
> - crm, opc1, opc2);
> + if (state == ARM_CP_STATE_AA32) {
> + /* Under Aarch32 CP registers can be common
> + * (same for secure and non-secure world) or banked.
> + */
> + add_cpreg_to_hashtable(cpu, r, opaque, state,
> + crm, opc1, opc2, !SCR_NS);
> + add_cpreg_to_hashtable(cpu, r, opaque, state,
> + crm, opc1, opc2, SCR_NS);
You may need to make one of the reginfos of type ARM_CP_NO_MIGRATE if
you add non-banked register here twice.
> + } else {
> + /* Aarch64 registers get mapped to non-secure
> instance
> + * of Aarch32 */
> + add_cpreg_to_hashtable(cpu, r, opaque, state,
> + crm, opc1, opc2, SCR_NS);
> + }
> }
> }
> }
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index f657389..30d9592 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -6968,7 +6968,7 @@ static int disas_neon_data_insn(CPUARMState * env,
> DisasContext *s, uint32_t ins
>
> static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t
> insn)
> {
> - int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
> + int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2, ns;
> const ARMCPRegInfo *ri;
>
> cpnum = (insn >> 8) & 0xf;
> @@ -7012,8 +7012,11 @@ static int disas_coproc_insn(CPUARMState * env,
> DisasContext *s, uint32_t insn)
> isread = (insn >> 20) & 1;
> rt = (insn >> 12) & 0xf;
>
> + /* Monitor mode is always treated as secure but cp register reads/writes
> + * can access secure and non-secure instances using SCR.NS bit*/
> + ns = IS_NS(s) ? 1 : !USE_SECURE_REG(env);
> ri = get_arm_cp_reginfo(s->cp_regs,
> - ENCODE_CP_REG(cpnum, is64, crn, crm, opc1,
> opc2));
> + ENCODE_CP_REG(cpnum, is64, crn, crm, opc1, opc2, ns));
> if (ri) {
> /* Check access permissions */
> if (!cp_access_ok(s->current_pl, ri, isread)) {
> @@ -7200,12 +7203,16 @@ static int disas_coproc_insn(CPUARMState * env,
> DisasContext *s, uint32_t insn)
> */
> if (is64) {
> qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
> - "64 bit system register cp:%d opc1: %d crm:%d\n",
> - isread ? "read" : "write", cpnum, opc1, crm);
> + "64 bit system register cp:%d opc1: %d crm:%d "
> + "(%s)\n",
> + isread ? "read" : "write", cpnum, opc1, crm,
> + ns ? "non-secure" : "secure");
> } else {
> qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
> - "system register cp:%d opc1:%d crn:%d crm:%d
> opc2:%d\n",
> - isread ? "read" : "write", cpnum, opc1, crn, crm,
> opc2);
> + "system register cp:%d opc1:%d crn:%d crm:%d opc2:%d "
> + "(%s)\n",
> + isread ? "read" : "write", cpnum, opc1, crn, crm, opc2,
> + ns ? "non-secure" : "secure");
> }
>
> return 1;
