On 04/09/2014 05:54 AM, Claudio Fontana wrote: > During testing I found this patch causes a regression for big endian targets > (sparc). > > Can you take a look? > I think it might be related to the extended form of the REV instruction > needing > an additional 0x400. See below.
You're right. It's disassembling as "rev32 x0, x0". Bizzarely, sparc32 bios was working. I guess it only uses 64-bit load/store for ldd/std for register pair save and restore. And since we rev'ed them the same way for load/store, it worked. Uploading a full mipseb system image to test now. r~
