On Di, 2013-11-26 at 16:04 +0200, Michael S. Tsirkin wrote:
> On Tue, Nov 26, 2013 at 12:00:51PM +0100, Gerd Hoffmann wrote:
> > Hi,
> >
> > > I think it's down to other qemu bugs (such as _CRS not covering
> > > all of PCI memory), we shall just fix them.
> >
> > i.e. the attached patch should fixup things.
> >
> > cheers,
> > Gerd
> >
>
> Yes, I think it's a start. Q35 is a bit harder because of the MMIO
> region.
??? Do you mean mmconfig? That can live inside the window. So
something like the attached patch should work in theory. In practice it
hasn't the expected effect for some reason ...
> Do we want to tweak end too? There's all kind of
> stuff there so need to be careful ...
I'd leave the end as-is, at the ioapic address.
cheers,
Gerd
>From 3d01b6c46fbf655bdb9b4f7ca427f40959b05d31 Mon Sep 17 00:00:00 2001
From: Gerd Hoffmann <kra...@redhat.com>
Date: Tue, 26 Nov 2013 16:18:04 +0100
Subject: [PATCH] [wip] q35: fix 32bit pci hole
Signed-off-by: Gerd Hoffmann <kra...@redhat.com>
---
hw/pci-host/q35.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index c043998..8d47bf9 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -179,15 +179,6 @@ static void q35_host_initfn(Object *obj)
object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int",
q35_host_get_mmcfg_size,
NULL, NULL, NULL, NULL);
-
- /* Leave enough space for the biggest MCFG BAR */
- /* TODO: this matches current bios behaviour, but
- * it's not a power of two, which means an MTRR
- * can't cover it exactly.
- */
- s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
- MCH_HOST_BRIDGE_PCIEXBAR_MAX;
- s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
}
static const TypeInfo q35_host_info = {
@@ -365,6 +356,8 @@ static int mch_init(PCIDevice *d)
0x100000000ULL - mch->below_4g_mem_size);
memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size,
&mch->pci_hole);
+ mch->pci_info.w32.begin = mch->below_4g_mem_size;
+ mch->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
pci_hole64_size = pci_host_get_hole64_size(mch->pci_hole64_size);
pc_init_pci64_hole(&mch->pci_info, 0x100000000ULL + mch->above_4g_mem_size,
--
1.8.3.1
