Hi,
> I think it's down to other qemu bugs (such as _CRS not covering
> all of PCI memory), we shall just fix them.
i.e. the attached patch should fixup things.
cheers,
Gerd
>From a81b8d66e24fd298ce7654d424a378337e6cf132 Mon Sep 17 00:00:00 2001
From: Gerd Hoffmann <kra...@redhat.com>
Date: Tue, 26 Nov 2013 11:46:11 +0100
Subject: [PATCH] piix: fix 32bit pci hole
Make the 32bit pci hole start at end of ram, so all possible address
space is covered. Of course the firmware can use less than that.
Leaving space unused is no problem, mapping pci bars outside the
hole causes problems though.
Signed-off-by: Gerd Hoffmann <kra...@redhat.com>
---
hw/pci-host/piix.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index edc974e..1414a2b 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -345,15 +345,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
f->ram_memory = ram_memory;
i440fx = I440FX_PCI_HOST_BRIDGE(dev);
- /* Set PCI window size the way seabios has always done it. */
- /* Power of 2 so bios can cover it with a single MTRR */
- if (ram_size <= 0x80000000) {
- i440fx->pci_info.w32.begin = 0x80000000;
- } else if (ram_size <= 0xc0000000) {
- i440fx->pci_info.w32.begin = 0xc0000000;
- } else {
- i440fx->pci_info.w32.begin = 0xe0000000;
- }
+ i440fx->pci_info.w32.begin = ram_size;
memory_region_init_alias(&f->pci_hole, OBJECT(d), "pci-hole", f->pci_address_space,
pci_hole_start, pci_hole_size);
--
1.8.3.1
