Re: [PATCH v4 09/11] target/loongarch: CPU enable msg interrupts.

[gaosong]

在 2025/7/10 上午10:43, Bibo Mao 写道:

On 2025/7/3 下午5:26, Song Gao wrote:

when loongarch cpu set irq is INT_AVEC, we need set CSR_ESTAT.MSGINT bit
and CSR_ECFG.MSGINT bit.

Signed-off-by: Song Gao <gaos...@loongson.cn>
---
  target/loongarch/cpu-csr.h |  6 ++++--
  target/loongarch/cpu.c     | 10 ++++++++++
  2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index 4792677086..6ec13d13d1 100644
--- a/target/loongarch/cpu-csr.h
+++ b/target/loongarch/cpu-csr.h
@@ -34,11 +34,13 @@ FIELD(CSR_MISC, ALCL, 12, 4)
  FIELD(CSR_MISC, DWPL, 16, 3)
    #define LOONGARCH_CSR_ECFG           0x4 /* Exception config */
-FIELD(CSR_ECFG, LIE, 0, 13)
+FIELD(CSR_ECFG, LIE, 0, 15)        /*bit 15 is msg interrupt enabled */
+FIELD(CSR_ECFG, MSGINT, 14, 1)
  FIELD(CSR_ECFG, VS, 16, 3)
    #define LOONGARCH_CSR_ESTAT          0x5 /* Exception status */
-FIELD(CSR_ESTAT, IS, 0, 13)
+FIELD(CSR_ESTAT, IS, 0, 15)        /*bit 15 is msg interrupt enabled */
+FIELD(CSR_ESTAT, MSGINT, 14, 1)
  FIELD(CSR_ESTAT, ECODE, 16, 6)
  FIELD(CSR_ESTAT, ESUBCODE, 22, 9)
  diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index abad84c054..89ea221347 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c

@@ -127,6 +127,16 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int level)

          return;
      }
  +    /* do INTC_AVEC irqs */
+    if (irq == INT_AVEC) {
+        for (int i = 256; i >= 0; i--) {
+            if (test_bit(i, &(env->CSR_MSGIS[i / 64]))) {

+                env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, MSGINT, 1); +                env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, MSGINT, 1);

why is register CSR_ECFG modified here?

I understand now,  we do'nt need set ecfg bit on qemu.

+            }
+        }

This piece of code should be put in sentences within tcg_enabled().

There may be duplicated function call with register CSR_ESTAT.
How about something like this?
  irq = find_first_bit(env->CSR_MSGIS, 256);
  if (irq < 256) {
    env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, MSGINT, 1);
  }

+    }
+
      if (kvm_enabled()) {
          kvm_loongarch_set_interrupt(cpu, irq, level);
      } else if (tcg_enabled()) {

modification estat should be put here.

I will correct on v5.
Thanks.
Song Gao

Regards
Bibo Mao