Re: [PATCH v4 10/11] target/loongarch:Implement csrrd CSR_MSGIR register

[Bibo Mao]

On 2025/7/3 下午5:26, Song Gao wrote:

implement the read-clear feature for CSR_MSGIR register.

Signed-off-by: Song Gao <gaos...@loongson.cn>
---
  target/loongarch/csr.c                        |  5 +++++
  target/loongarch/tcg/csr_helper.c             | 22 +++++++++++++++++++
  target/loongarch/tcg/helper.h                 |  1 +
  .../tcg/insn_trans/trans_privileged.c.inc     |  1 +
  4 files changed, 29 insertions(+)

diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c
index 7ea0a30450..f973780bba 100644
--- a/target/loongarch/csr.c
+++ b/target/loongarch/csr.c
@@ -97,6 +97,11 @@ static CSRInfo csr_info[] = {
      CSR_OFF(DBG),
      CSR_OFF(DERA),
      CSR_OFF(DSAVE),
+    CSR_OFF_ARRAY(MSGIS, 0),
+    CSR_OFF_ARRAY(MSGIS, 1),
+    CSR_OFF_ARRAY(MSGIS, 2),
+    CSR_OFF_ARRAY(MSGIS, 3),
+    CSR_OFF(MSGIR),
  };

CSRInfo *get_csr(unsigned int csr_num)

diff --git a/target/loongarch/tcg/csr_helper.c 
b/target/loongarch/tcg/csr_helper.c
index 2942d7feb8..29eb2d13c8 100644
--- a/target/loongarch/tcg/csr_helper.c
+++ b/target/loongarch/tcg/csr_helper.c
@@ -68,6 +68,28 @@ target_ulong helper_csrrd_tval(CPULoongArchState *env)
      return cpu_loongarch_get_constant_timer_ticks(cpu);
  }

+target_ulong helper_csrrd_msgir(CPULoongArchState *env)

+{
+    int irq, new;
+
+    irq = find_first_bit(env->CSR_MSGIS, 256);
+    if (irq < 256) {
+        clear_bit(irq, env->CSR_MSGIS);
+        new = find_first_bit(env->CSR_MSGIS, 256);
+        if (new < 256) {
+            return irq;
+        }
+
+        env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, MSGINT, 0);
+        env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, MSGINT, 0);

CSR_ECFG should not be modifed here.

+    } else {
+        /* bit 31 set 1 for no invalid irq */
+        irq = -1;

How about irq = BIT(31), the other bits keeps zero except bit 31?

Regards
Bibo Mao

+    }
+
+    return irq;
+}
+
  target_ulong helper_csrwr_estat(CPULoongArchState *env, target_ulong val)
  {
      int64_t old_v = env->CSR_ESTAT;
diff --git a/target/loongarch/tcg/helper.h b/target/loongarch/tcg/helper.h
index 1d5cb0198c..db57dbfc16 100644
--- a/target/loongarch/tcg/helper.h
+++ b/target/loongarch/tcg/helper.h
@@ -100,6 +100,7 @@ DEF_HELPER_1(rdtime_d, i64, env)
  DEF_HELPER_1(csrrd_pgd, i64, env)
  DEF_HELPER_1(csrrd_cpuid, i64, env)
  DEF_HELPER_1(csrrd_tval, i64, env)
+DEF_HELPER_1(csrrd_msgir, i64, env)
  DEF_HELPER_2(csrwr_stlbps, i64, env, tl)
  DEF_HELPER_2(csrwr_estat, i64, env, tl)
  DEF_HELPER_2(csrwr_asid, i64, env, tl)
diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc 
b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
index ecbfe23b63..2619b5342b 100644
--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
@@ -83,6 +83,7 @@ void loongarch_csr_translate_init(void)
      SET_CSR_FUNC(TCFG,  NULL, gen_helper_csrwr_tcfg);
      SET_CSR_FUNC(TVAL,  gen_helper_csrrd_tval, NULL);
      SET_CSR_FUNC(TICLR, NULL, gen_helper_csrwr_ticlr);
+    SET_CSR_FUNC(MSGIR, gen_helper_csrrd_msgir, NULL);
  }
  #undef SET_CSR_FUNC