Hi Bibo,
On Thu, Apr 24, 2025 at 10:32 AM bibo mao <maob...@loongson.cn> wrote:
>
>
>
> On 2025/4/24 上午10:11, WANG Rui wrote:
> > Hi Song,
> >
> > On Thu, Apr 24, 2025 at 9:40 AM gaosong <gaos...@loongson.cn> wrote:
> >>
> >> 在 2025/4/18 下午4:45, bibo mao 写道:
> >>>
> >>>
> >>> On 2025/4/18 下午4:21, WANG Rui wrote:
> >>>> This patch replaces uses of the generic TRANS macro with TRANS64 for
> >>>> instructions that are only valid when 64-bit support is available.
> >>>>
> >>>> This improves correctness and avoids potential assertion failures or
> >>>> undefined behavior during translation on 32-bit-only configurations.
> >>>>
> >>>> Signed-off-by: WANG Rui <wang...@loongson.cn>
> >>>> ---
> >>>> .../tcg/insn_trans/trans_atomic.c.inc | 36 +++++++++----------
> >>>> .../tcg/insn_trans/trans_extra.c.inc | 8 +++--
> >>>> .../tcg/insn_trans/trans_privileged.c.inc | 4 +--
> >>>> .../tcg/insn_trans/trans_shift.c.inc | 4 +--
> >>>> .../loongarch/tcg/insn_trans/trans_vec.c.inc | 16 ++++-----
> >>>> target/loongarch/translate.h | 4 +++
> >>>> 6 files changed, 40 insertions(+), 32 deletions(-)
> >>>>
> >>>> diff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
> >>>> b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
> >>>> index 3d70d75941..77eeedbc42 100644
> >>>> --- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
> >>>> +++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
> >>>> @@ -74,38 +74,38 @@ TRANS(sc_w, ALL, gen_sc, MO_TESL)
> >>>> TRANS(ll_d, 64, gen_ll, MO_TEUQ)
> >>>> TRANS(sc_d, 64, gen_sc, MO_TEUQ)
> >>>> TRANS(amswap_w, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
> >>>> -TRANS(amswap_d, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
> >>>> +TRANS64(amswap_d, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
> >>>> TRANS(amadd_w, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
> >>>> -TRANS(amadd_d, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
> >>>> +TRANS64(amadd_d, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
> >>>> TRANS(amand_w, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
> >>>> -TRANS(amand_d, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
> >>>> +TRANS64(amand_d, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
> >>>> TRANS(amor_w, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
> >>>> -TRANS(amor_d, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
> >>>> +TRANS64(amor_d, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
> >>>> TRANS(amxor_w, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
> >>>> -TRANS(amxor_d, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
> >>>> +TRANS64(amxor_d, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
> >>>> TRANS(ammax_w, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
> >>>> -TRANS(ammax_d, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
> >>>> +TRANS64(ammax_d, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
> >>>> TRANS(ammin_w, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
> >>>> -TRANS(ammin_d, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
> >>>> +TRANS64(ammin_d, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
> >>>> TRANS(ammax_wu, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
> >>>> -TRANS(ammax_du, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
> >>>> +TRANS64(ammax_du, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
> >>>> TRANS(ammin_wu, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
> >>>> -TRANS(ammin_du, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
> >>>> +TRANS64(ammin_du, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
> >>>> TRANS(amswap_db_w, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
> >>>> -TRANS(amswap_db_d, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
> >>>> +TRANS64(amswap_db_d, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
> >>>> TRANS(amadd_db_w, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
> >>>> -TRANS(amadd_db_d, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
> >>>> +TRANS64(amadd_db_d, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
> >>>> TRANS(amand_db_w, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
> >>>> -TRANS(amand_db_d, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
> >>>> +TRANS64(amand_db_d, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
> >>>> TRANS(amor_db_w, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
> >>>> -TRANS(amor_db_d, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
> >>>> +TRANS64(amor_db_d, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
> >>>> TRANS(amxor_db_w, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
> >>>> -TRANS(amxor_db_d, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
> >>>> +TRANS64(amxor_db_d, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
> >>>> TRANS(ammax_db_w, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
> >>>> -TRANS(ammax_db_d, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
> >>>> +TRANS64(ammax_db_d, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
> >>>> TRANS(ammin_db_w, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
> >>>> -TRANS(ammin_db_d, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
> >>>> +TRANS64(ammin_db_d, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
> >>>> TRANS(ammax_db_wu, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
> >>>> -TRANS(ammax_db_du, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
> >>>> +TRANS64(ammax_db_du, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl,
> >>>> MO_TEUQ)
> >>>> TRANS(ammin_db_wu, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
> >>>> -TRANS(ammin_db_du, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
> >>>> +TRANS64(ammin_db_du, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl,
> >>>> MO_TEUQ)
> >>>> diff --git a/target/loongarch/tcg/insn_trans/trans_extra.c.inc
> >>>> b/target/loongarch/tcg/insn_trans/trans_extra.c.inc
> >>>> index eda3d6e561..298a80cff5 100644
> >>>> --- a/target/loongarch/tcg/insn_trans/trans_extra.c.inc
> >>>> +++ b/target/loongarch/tcg/insn_trans/trans_extra.c.inc
> >>>> @@ -69,6 +69,10 @@ static bool trans_rdtimeh_w(DisasContext *ctx,
> >>>> arg_rdtimeh_w *a)
> >>>> static bool trans_rdtime_d(DisasContext *ctx, arg_rdtime_d *a)
> >>>> {
> >>>> + if (!avail_64(ctx)) {
> >>>> + return false;
> >>>> + }
> >>>> +
> >>>> return gen_rdtime(ctx, a, 0, 0);
> >>>> }
> >>>> @@ -100,8 +104,8 @@ static bool gen_crc(DisasContext *ctx, arg_rrr *a,
> >>>> TRANS(crc_w_b_w, CRC, gen_crc, gen_helper_crc32, tcg_constant_tl(1))
> >>>> TRANS(crc_w_h_w, CRC, gen_crc, gen_helper_crc32, tcg_constant_tl(2))
> >>>> TRANS(crc_w_w_w, CRC, gen_crc, gen_helper_crc32, tcg_constant_tl(4))
> >>>> -TRANS(crc_w_d_w, CRC, gen_crc, gen_helper_crc32, tcg_constant_tl(8))
> >>>> +TRANS64(crc_w_d_w, CRC, gen_crc, gen_helper_crc32, tcg_constant_tl(8))
> >>>> TRANS(crcc_w_b_w, CRC, gen_crc, gen_helper_crc32c, tcg_constant_tl(1))
> >>>> TRANS(crcc_w_h_w, CRC, gen_crc, gen_helper_crc32c, tcg_constant_tl(2))
> >>>> TRANS(crcc_w_w_w, CRC, gen_crc, gen_helper_crc32c, tcg_constant_tl(4))
> >>>> -TRANS(crcc_w_d_w, CRC, gen_crc, gen_helper_crc32c, tcg_constant_tl(8))
> >>>> +TRANS64(crcc_w_d_w, CRC, gen_crc, gen_helper_crc32c,
> >>>> tcg_constant_tl(8))
> >>>> diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
> >>>> b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
> >>>> index ecbfe23b63..34cfab8879 100644
> >>>> --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
> >>>> +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
> >>>> @@ -233,11 +233,11 @@ static bool gen_iocsrwr(DisasContext *ctx,
> >>>> arg_rr *a,
> >>>> TRANS(iocsrrd_b, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_b)
> >>>> TRANS(iocsrrd_h, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_h)
> >>>> TRANS(iocsrrd_w, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_w)
> >>>> -TRANS(iocsrrd_d, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_d)
> >>>> +TRANS64(iocsrrd_d, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_d)
> >>>> TRANS(iocsrwr_b, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_b)
> >>>> TRANS(iocsrwr_h, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_h)
> >>>> TRANS(iocsrwr_w, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_w)
> >>>> -TRANS(iocsrwr_d, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_d)
> >>>> +TRANS64(iocsrwr_d, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_d)
> >>>> static void check_mmu_idx(DisasContext *ctx)
> >>>> {
> >>>> diff --git a/target/loongarch/tcg/insn_trans/trans_shift.c.inc
> >>>> b/target/loongarch/tcg/insn_trans/trans_shift.c.inc
> >>>> index 377307785a..136c4c8455 100644
> >>>> --- a/target/loongarch/tcg/insn_trans/trans_shift.c.inc
> >>>> +++ b/target/loongarch/tcg/insn_trans/trans_shift.c.inc
> >>>> @@ -78,7 +78,7 @@ TRANS(sra_w, ALL, gen_rrr, EXT_SIGN, EXT_NONE,
> >>>> EXT_SIGN, gen_sra_w)
> >>>> TRANS(sll_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d)
> >>>> TRANS(srl_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d)
> >>>> TRANS(sra_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d)
> >>>> -TRANS(rotr_w, 64, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w)
> >>>> +TRANS(rotr_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w)
> >>>> TRANS(rotr_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d)
> >>>> TRANS(slli_w, ALL, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl)
> >>>> TRANS(slli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl)
> >>>> @@ -86,5 +86,5 @@ TRANS(srli_w, ALL, gen_rri_c, EXT_ZERO, EXT_SIGN,
> >>>> tcg_gen_shri_tl)
> >>>> TRANS(srli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl)
> >>>> TRANS(srai_w, ALL, gen_rri_c, EXT_NONE, EXT_NONE, gen_sari_w)
> >>>> TRANS(srai_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl)
> >>>> -TRANS(rotri_w, 64, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)
> >>>> +TRANS(rotri_w, ALL, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)
> >>>> TRANS(rotri_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl)
> >>> The modification looks good to me.
> >>>
> >>>> diff --git a/target/loongarch/tcg/insn_trans/trans_vec.c.inc
> >>>> b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
> >>>> index dff92772ad..a6f5b346bb 100644
> >>>> --- a/target/loongarch/tcg/insn_trans/trans_vec.c.inc
> >>>> +++ b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
> >>>> @@ -4853,9 +4853,9 @@ static bool gen_g2x(DisasContext *ctx, arg_vr_i
> >>>> *a, MemOp mop,
> >>>> TRANS(vinsgr2vr_b, LSX, gen_g2v, MO_8, tcg_gen_st8_i64)
> >>>> TRANS(vinsgr2vr_h, LSX, gen_g2v, MO_16, tcg_gen_st16_i64)
> >>>> TRANS(vinsgr2vr_w, LSX, gen_g2v, MO_32, tcg_gen_st32_i64)
> >>>> -TRANS(vinsgr2vr_d, LSX, gen_g2v, MO_64, tcg_gen_st_i64)
> >>>> +TRANS64(vinsgr2vr_d, LSX, gen_g2v, MO_64, tcg_gen_st_i64)
> >>>> TRANS(xvinsgr2vr_w, LASX, gen_g2x, MO_32, tcg_gen_st32_i64)
> >>>> -TRANS(xvinsgr2vr_d, LASX, gen_g2x, MO_64, tcg_gen_st_i64)
> >>>> +TRANS64(xvinsgr2vr_d, LASX, gen_g2x, MO_64, tcg_gen_st_i64)
> >>> This looks good, only that I do not know whether it is necessary.
> >>> Can you conclude that LSX/LASX means that 64 bit is supported also?
> >>>
> >>> Song, what is your option?
> >>>
> >> I think LSX/LASX is enough
> >>
> >> Hi , WANG Rui
> >> why only these XXX_d vec instructions need TRANS64?
> >
> > As far as I know, although there are currently no LoongArch 32-bit
> > implementations that support LSX or LASX, the ISA itself does not
> > explicitly forbid such a combination. In other words, LSX/LASX is not
> > inherently tied to a 64-bit base architecture.
> I do not know. it will be better chip guys can give us the answer. LSX
> is 128bit vector instruction, LASX is 256bit vector instruction, I do
> not know how chip guys skip 64bit support and design another LSX/LASX
> instruction.
Actually, this point is clarified in the LoongArch Reference Manual --
Volume II. According to the first section of the document:
The implementation of LSX or LASX is independent of whether the base
architecture is LA32 or LA64. Except for a small number of
instructions that transfer 64-bit data between general-purpose and
vector registers -- which are only required on LA64 -- all other
vector extension instructions can be implemented on either LA32 or
LA64 processors.
>
> > Given this, I chose to mark certain vector instructions --
> > specifically those that access general-purpose registers using 64-bit
> > data width (such as the _d variants) -- as requiring TRANS64. This
> > ensures the backedn correctly handles them in case LSX/LASX support
> > apperars on a 32-bit target in the future.
> If LSX/LASX support will be added 32-bit target, we need indicator
> showing its capability firstly, and then add partial LSX/LASX support,
> rather than do it now.
>
> We are SW developers, rather than chip designers -:)
You're absolutely right -- we're not chip designers -:) But in a way,
what we're doing with software is building a machine that simulates
the ISA. With just a few dozen lines of code, we can easily create a
32-bit virtual CPU that supports vector features. This kind of setup
is already happening in practice, especially for developers using QEMU
to validate 32-bit system software stacks.
That's why I believe it's worthwhile to introduce the necessary
constraints now, to prevent certain vector instructions -- those that
implicitly rely on 64-bit GPR access -- from silently working in
environments where they shouldn't. This patch aims to ensure
correctness and consistency in such simulated or future scenarios.
Regards,
Rui
>
> Regards
> Bibo Mao
> >
> > Let me know if you have other suggestions or if I misunderstood somehing.
> >
> > Regards,
> > Rui
> >
> >>
> >> I just pick up patch1, 2 to loongarch-next .
> >>
> >> Thanks.
> >> Song Gao
> >>> Regards
> >>> Bibo Mao
> >>>> static bool gen_v2g_vl(DisasContext *ctx, arg_rv_i *a, uint32_t
> >>>> oprsz, MemOp mop,
> >>>> void (*func)(TCGv, TCGv_ptr, tcg_target_long))
> >>>> @@ -4886,15 +4886,15 @@ static bool gen_x2g(DisasContext *ctx,
> >>>> arg_rv_i *a, MemOp mop,
> >>>> TRANS(vpickve2gr_b, LSX, gen_v2g, MO_8, tcg_gen_ld8s_i64)
> >>>> TRANS(vpickve2gr_h, LSX, gen_v2g, MO_16, tcg_gen_ld16s_i64)
> >>>> TRANS(vpickve2gr_w, LSX, gen_v2g, MO_32, tcg_gen_ld32s_i64)
> >>>> -TRANS(vpickve2gr_d, LSX, gen_v2g, MO_64, tcg_gen_ld_i64)
> >>>> +TRANS64(vpickve2gr_d, LSX, gen_v2g, MO_64, tcg_gen_ld_i64)
> >>>> TRANS(vpickve2gr_bu, LSX, gen_v2g, MO_8, tcg_gen_ld8u_i64)
> >>>> TRANS(vpickve2gr_hu, LSX, gen_v2g, MO_16, tcg_gen_ld16u_i64)
> >>>> TRANS(vpickve2gr_wu, LSX, gen_v2g, MO_32, tcg_gen_ld32u_i64)
> >>>> -TRANS(vpickve2gr_du, LSX, gen_v2g, MO_64, tcg_gen_ld_i64)
> >>>> +TRANS64(vpickve2gr_du, LSX, gen_v2g, MO_64, tcg_gen_ld_i64)
> >>>> TRANS(xvpickve2gr_w, LASX, gen_x2g, MO_32, tcg_gen_ld32s_i64)
> >>>> -TRANS(xvpickve2gr_d, LASX, gen_x2g, MO_64, tcg_gen_ld_i64)
> >>>> +TRANS64(xvpickve2gr_d, LASX, gen_x2g, MO_64, tcg_gen_ld_i64)
> >>>> TRANS(xvpickve2gr_wu, LASX, gen_x2g, MO_32, tcg_gen_ld32u_i64)
> >>>> -TRANS(xvpickve2gr_du, LASX, gen_x2g, MO_64, tcg_gen_ld_i64)
> >>>> +TRANS64(xvpickve2gr_du, LASX, gen_x2g, MO_64, tcg_gen_ld_i64)
> >>>> static bool gvec_dup_vl(DisasContext *ctx, arg_vr *a,
> >>>> uint32_t oprsz, MemOp mop)
> >>>> @@ -4923,11 +4923,11 @@ static bool gvec_dupx(DisasContext *ctx,
> >>>> arg_vr *a, MemOp mop)
> >>>> TRANS(vreplgr2vr_b, LSX, gvec_dup, MO_8)
> >>>> TRANS(vreplgr2vr_h, LSX, gvec_dup, MO_16)
> >>>> TRANS(vreplgr2vr_w, LSX, gvec_dup, MO_32)
> >>>> -TRANS(vreplgr2vr_d, LSX, gvec_dup, MO_64)
> >>>> +TRANS64(vreplgr2vr_d, LSX, gvec_dup, MO_64)
> >>>> TRANS(xvreplgr2vr_b, LASX, gvec_dupx, MO_8)
> >>>> TRANS(xvreplgr2vr_h, LASX, gvec_dupx, MO_16)
> >>>> TRANS(xvreplgr2vr_w, LASX, gvec_dupx, MO_32)
> >>>> -TRANS(xvreplgr2vr_d, LASX, gvec_dupx, MO_64)
> >>>> +TRANS64(xvreplgr2vr_d, LASX, gvec_dupx, MO_64)
> >>>> static bool trans_vreplvei_b(DisasContext *ctx, arg_vv_i *a)
> >>>> {
> >>>> diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
> >>>> index 018dc5eb17..bbe015ba57 100644
> >>>> --- a/target/loongarch/translate.h
> >>>> +++ b/target/loongarch/translate.h
> >>>> @@ -14,6 +14,10 @@
> >>>> static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
> >>>> { return avail_##AVAIL(ctx) && FUNC(ctx, a, __VA_ARGS__); }
> >>>> +#define TRANS64(NAME, AVAIL, FUNC, ...) \
> >>>> + static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
> >>>> + { return avail_64(ctx) && avail_##AVAIL(ctx) && FUNC(ctx, a,
> >>>> __VA_ARGS__); }
> >>>> +
> >>>> #define avail_ALL(C) true
> >>>> #define avail_64(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, ARCH) == \
> >>>> CPUCFG1_ARCH_LA64)
> >>>>
> >>
>
