On 2025/4/18 下午4:21, WANG Rui wrote:
The BCEQZ and BCNEZ instructions depend on access to condition codes from floating-point comparisons. Previously, these instructions were unconditionally enabled for 64-bit targets. This patch updates their translation to be gated under the `FP` feature flag instead, ensuring they are only available when the floating-point unit is present. This improves correctness for CPUs lacking floating-point support. Signed-off-by: WANG Rui <wang...@loongson.cn> --- target/loongarch/tcg/insn_trans/trans_branch.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/loongarch/tcg/insn_trans/trans_branch.c.inc b/target/loongarch/tcg/insn_trans/trans_branch.c.inc index 221e5159db..f94c1f37ab 100644 --- a/target/loongarch/tcg/insn_trans/trans_branch.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_branch.c.inc @@ -80,5 +80,5 @@ TRANS(bltu, ALL, gen_rr_bc, TCG_COND_LTU) TRANS(bgeu, ALL, gen_rr_bc, TCG_COND_GEU) TRANS(beqz, ALL, gen_rz_bc, TCG_COND_EQ) TRANS(bnez, ALL, gen_rz_bc, TCG_COND_NE) -TRANS(bceqz, 64, gen_cz_bc, TCG_COND_EQ) -TRANS(bcnez, 64, gen_cz_bc, TCG_COND_NE) +TRANS(bceqz, FP, gen_cz_bc, TCG_COND_EQ) +TRANS(bcnez, FP, gen_cz_bc, TCG_COND_NE)
Reviewed-by: Bibo Mao <maob...@loongson.cn>
