On Sun, Apr 6, 2025 at 5:03 PM Paolo Bonzini <pbonz...@redhat.com> wrote:
>
> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 39 ++++++++++++++++-----------------------
> 1 file changed, 16 insertions(+), 23 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index e72ebdf206a..fe1edf3be97 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -691,28 +691,6 @@ static void rv32_sifive_u_cpu_init(Object *obj)
> cpu->cfg.mmu = true;
> cpu->cfg.pmp = true;
> }
> -
> -static void rv32_ibex_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - RISCVCPU *cpu = RISCV_CPU(obj);
> -
> - riscv_cpu_set_misa_ext(env, RVI | RVM | RVC | RVU);
> - env->priv_ver = PRIV_VERSION_1_12_0;
> -#ifndef CONFIG_USER_ONLY
> - set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> -#endif
> - /* inherited from parent obj via riscv_cpu_init() */
> - cpu->cfg.ext_zifencei = true;
> - cpu->cfg.ext_zicsr = true;
> - cpu->cfg.pmp = true;
> - cpu->cfg.ext_smepmp = true;
> -
> - cpu->cfg.ext_zba = true;
> - cpu->cfg.ext_zbb = true;
> - cpu->cfg.ext_zbc = true;
> - cpu->cfg.ext_zbs = true;
> -}
> #endif
>
> static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
> @@ -3173,7 +3151,22 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .misa_mxl_max = MXL_RV32,
> ),
>
> - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32,
> rv32_ibex_cpu_init),
> + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_IBEX, TYPE_RISCV_VENDOR_CPU,
> + .misa_mxl_max = MXL_RV32,
> + .misa_ext = RVI | RVM | RVC | RVU,
> + .priv_spec = PRIV_VERSION_1_12_0,
> + .cfg.max_satp_mode = VM_1_10_MBARE,
> + .cfg.ext_zifencei = true,
> + .cfg.ext_zicsr = true,
> + .cfg.pmp = true,
> + .cfg.ext_smepmp = true,
> +
> + .cfg.ext_zba = true,
> + .cfg.ext_zbb = true,
> + .cfg.ext_zbc = true,
> + .cfg.ext_zbs = true
> + ),
> +
> DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E,
> .misa_mxl_max = MXL_RV32
> ),
> --
> 2.49.0
>
