On Sun, Apr 6, 2025 at 5:03 PM Paolo Bonzini <pbonz...@redhat.com> wrote:
>
> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 79 +++++++++++++++++++-----------------------
> 2 files changed, 37 insertions(+), 43 deletions(-)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 0f9be15e47b..1ee05eb393d 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -48,6 +48,7 @@
> #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
> #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
> #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
> +#define TYPE_RISCV_CPU_SIFIVE_U RISCV_CPU_TYPE_NAME("sifive-u")
> #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
> #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
> #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index fe1edf3be97..6f516163486 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -441,8 +441,8 @@ const char *satp_mode_str(uint8_t satp_mode, bool
> is_32_bit)
> g_assert_not_reached();
> }
>
> -static void set_satp_mode_max_supported(RISCVCPU *cpu,
> - int satp_mode)
> +static void __attribute__((unused))
> +set_satp_mode_max_supported(RISCVCPU *cpu, int satp_mode)
> {
> bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
> const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
> @@ -487,23 +487,6 @@ static void set_satp_mode_default_map(RISCVCPU *cpu)
> #endif
>
> #if defined(TARGET_RISCV64)
> -static void rv64_sifive_u_cpu_init(Object *obj)
> -{
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> - riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS |
> RVU);
> - env->priv_ver = PRIV_VERSION_1_10_0;
> -#ifndef CONFIG_USER_ONLY
> - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
> -#endif
> -
> - /* inherited from parent obj via riscv_cpu_init() */
> - cpu->cfg.ext_zifencei = true;
> - cpu->cfg.ext_zicsr = true;
> - cpu->cfg.mmu = true;
> - cpu->cfg.pmp = true;
> -}
> -
> static void rv64_thead_c906_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -672,27 +655,6 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
>
> #endif /* !TARGET_RISCV64 */
>
> -#if defined(TARGET_RISCV32) || \
> - (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
> -
> -static void rv32_sifive_u_cpu_init(Object *obj)
> -{
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> - riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS |
> RVU);
> - env->priv_ver = PRIV_VERSION_1_10_0;
> -#ifndef CONFIG_USER_ONLY
> - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
> -#endif
> -
> - /* inherited from parent obj via riscv_cpu_init() */
> - cpu->cfg.ext_zifencei = true;
> - cpu->cfg.ext_zicsr = true;
> - cpu->cfg.mmu = true;
> - cpu->cfg.pmp = true;
> -}
> -#endif
> -
> static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
> {
> ObjectClass *oc;
> @@ -2925,6 +2887,17 @@ static void riscv_cpu_class_base_init(ObjectClass *c,
> void *data)
> if (def->misa_mxl_max) {
> assert(def->misa_mxl_max <= MXL_RV128);
> mcc->def->misa_mxl_max = def->misa_mxl_max;
> +
> +#ifndef CONFIG_USER_ONLY
> + /*
> + * Hack to simplify CPU class hierarchies that include both 32-
> and
> + * 64-bit models: reduce SV39/48/57/64 to SV32 for 32-bit models.
> + */
> + if (mcc->def->misa_mxl_max == MXL_RV32 &&
> + !valid_vm_1_10_32[mcc->def->cfg.max_satp_mode]) {
> + mcc->def->cfg.max_satp_mode = VM_1_10_SV32;
> + }
> +#endif
> }
> if (def->priv_spec != RISCV_PROFILE_ATTR_UNUSED) {
> assert(def->priv_spec <= PRIV_VERSION_LATEST);
> @@ -3144,6 +3117,17 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .cfg.pmp = true
> ),
>
> + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U, TYPE_RISCV_VENDOR_CPU,
> + .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU,
> + .priv_spec = PRIV_VERSION_1_10_0,
> +
> + .cfg.max_satp_mode = VM_1_10_SV39,
> + .cfg.ext_zifencei = true,
> + .cfg.ext_zicsr = true,
> + .cfg.mmu = true,
> + .cfg.pmp = true
> + ),
> +
> #if defined(TARGET_RISCV32) || \
> (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
> DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU,
> @@ -3175,7 +3159,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .misa_ext = RVF, /* IMAFCU */
> ),
>
> - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32,
> rv32_sifive_u_cpu_init),
> + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U34, TYPE_RISCV_CPU_SIFIVE_U,
> + .misa_mxl_max = MXL_RV32,
> + ),
>
> DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU,
> .misa_mxl_max = MXL_RV32,
> @@ -3203,8 +3189,15 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E51, TYPE_RISCV_CPU_SIFIVE_E,
> .misa_mxl_max = MXL_RV64
> ),
> - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64,
> rv64_sifive_u_cpu_init),
> - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64,
> rv64_sifive_u_cpu_init),
> +
> + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U54, TYPE_RISCV_CPU_SIFIVE_U,
> + .misa_mxl_max = MXL_RV64,
> + ),
> +
> + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SHAKTI_C, TYPE_RISCV_CPU_SIFIVE_U,
> + .misa_mxl_max = MXL_RV64,
> + ),
> +
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64,
> rv64_thead_c906_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64,
> rv64_tt_ascalon_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64,
> rv64_veyron_v1_cpu_init),
> --
> 2.49.0
>
