On Sun, Apr 6, 2025 at 5:03 PM Paolo Bonzini <pbonz...@redhat.com> wrote:
>
> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 74 ++++++++++++------------------------------
> 2 files changed, 21 insertions(+), 54 deletions(-)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 4cfdb74891e..0f9be15e47b 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -44,6 +44,7 @@
> #define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64")
> #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
> #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
> +#define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive-e")
> #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
> #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
> #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 73c815d22e9..e72ebdf206a 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -504,23 +504,6 @@ static void rv64_sifive_u_cpu_init(Object *obj)
> cpu->cfg.pmp = true;
> }
>
> -static void rv64_sifive_e_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - RISCVCPU *cpu = RISCV_CPU(obj);
> -
> - riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU);
> - env->priv_ver = PRIV_VERSION_1_10_0;
> -#ifndef CONFIG_USER_ONLY
> - set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> -#endif
> -
> - /* inherited from parent obj via riscv_cpu_init() */
> - cpu->cfg.ext_zifencei = true;
> - cpu->cfg.ext_zicsr = true;
> - cpu->cfg.pmp = true;
> -}
> -
> static void rv64_thead_c906_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -709,23 +692,6 @@ static void rv32_sifive_u_cpu_init(Object *obj)
> cpu->cfg.pmp = true;
> }
>
> -static void rv32_sifive_e_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - RISCVCPU *cpu = RISCV_CPU(obj);
> -
> - riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU);
> - env->priv_ver = PRIV_VERSION_1_10_0;
> -#ifndef CONFIG_USER_ONLY
> - set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> -#endif
> -
> - /* inherited from parent obj via riscv_cpu_init() */
> - cpu->cfg.ext_zifencei = true;
> - cpu->cfg.ext_zicsr = true;
> - cpu->cfg.pmp = true;
> -}
> -
> static void rv32_ibex_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -747,23 +713,6 @@ static void rv32_ibex_cpu_init(Object *obj)
> cpu->cfg.ext_zbc = true;
> cpu->cfg.ext_zbs = true;
> }
> -
> -static void rv32_imafcu_nommu_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - RISCVCPU *cpu = RISCV_CPU(obj);
> -
> - riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVC | RVU);
> - env->priv_ver = PRIV_VERSION_1_10_0;
> -#ifndef CONFIG_USER_ONLY
> - set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> -#endif
> -
> - /* inherited from parent obj via riscv_cpu_init() */
> - cpu->cfg.ext_zifencei = true;
> - cpu->cfg.ext_zicsr = true;
> - cpu->cfg.pmp = true;
> -}
> #endif
>
> static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
> @@ -3208,6 +3157,15 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> #endif
> ),
>
> + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E, TYPE_RISCV_VENDOR_CPU,
> + .misa_ext = RVI | RVM | RVA | RVC | RVU,
> + .priv_spec = PRIV_VERSION_1_10_0,
> + .cfg.max_satp_mode = VM_1_10_MBARE,
> + .cfg.ext_zifencei = true,
> + .cfg.ext_zicsr = true,
> + .cfg.pmp = true
> + ),
> +
> #if defined(TARGET_RISCV32) || \
> (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
> DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU,
> @@ -3216,8 +3174,14 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> ),
>
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32,
> rv32_ibex_cpu_init),
> - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32,
> rv32_sifive_e_cpu_init),
> - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32,
> rv32_imafcu_nommu_cpu_init),
> + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E,
> + .misa_mxl_max = MXL_RV32
> + ),
> + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E34, TYPE_RISCV_CPU_SIFIVE_E,
> + .misa_mxl_max = MXL_RV32,
> + .misa_ext = RVF, /* IMAFCU */
> + ),
> +
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32,
> rv32_sifive_u_cpu_init),
>
> DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU,
> @@ -3243,7 +3207,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .misa_mxl_max = MXL_RV64,
> ),
>
> - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64,
> rv64_sifive_e_cpu_init),
> + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E51, TYPE_RISCV_CPU_SIFIVE_E,
> + .misa_mxl_max = MXL_RV64
> + ),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64,
> rv64_sifive_u_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64,
> rv64_sifive_u_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64,
> rv64_thead_c906_cpu_init),
> --
> 2.49.0
>
