On Sun, Apr 6, 2025 at 5:03 PM Paolo Bonzini <pbonz...@redhat.com> wrote:
>
> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 113 ++++++++++++---------------------------------
> 1 file changed, 30 insertions(+), 83 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 2ea203d97b7..73c815d22e9 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -486,38 +486,7 @@ static void set_satp_mode_default_map(RISCVCPU *cpu)
> }
> #endif
>
> -static void riscv_max_cpu_init(Object *obj)
> -{
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> -
> - cpu->cfg.mmu = true;
> - cpu->cfg.pmp = true;
> -
> - env->priv_ver = PRIV_VERSION_LATEST;
> -#ifndef CONFIG_USER_ONLY
> - set_satp_mode_max_supported(RISCV_CPU(obj),
> - riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
> - VM_1_10_SV32 : VM_1_10_SV57);
> -#endif
> -}
> -
> #if defined(TARGET_RISCV64)
> -static void rv64_base_cpu_init(Object *obj)
> -{
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> -
> - cpu->cfg.mmu = true;
> - cpu->cfg.pmp = true;
> -
> - /* Set latest version of privileged specification */
> - env->priv_ver = PRIV_VERSION_LATEST;
> -#ifndef CONFIG_USER_ONLY
> - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
> -#endif
> -}
> -
> static void rv64_sifive_u_cpu_init(Object *obj)
> {
> RISCVCPU *cpu = RISCV_CPU(obj);
> @@ -718,43 +687,11 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
> #endif
> }
>
> -#ifdef CONFIG_TCG
> -static void rv128_base_cpu_init(Object *obj)
> -{
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> -
> - cpu->cfg.mmu = true;
> - cpu->cfg.pmp = true;
> -
> - /* Set latest version of privileged specification */
> - env->priv_ver = PRIV_VERSION_LATEST;
> -#ifndef CONFIG_USER_ONLY
> - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
> -#endif
> -}
> -#endif /* CONFIG_TCG */
> -
> #endif /* !TARGET_RISCV64 */
>
> #if defined(TARGET_RISCV32) || \
> (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
>
> -static void rv32_base_cpu_init(Object *obj)
> -{
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> -
> - cpu->cfg.mmu = true;
> - cpu->cfg.pmp = true;
> -
> - /* Set latest version of privileged specification */
> - env->priv_ver = PRIV_VERSION_LATEST;
> -#ifndef CONFIG_USER_ONLY
> - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
> -#endif
> -}
> -
> static void rv32_sifive_u_cpu_init(Object *obj)
> {
> RISCVCPU *cpu = RISCV_CPU(obj);
> @@ -3172,19 +3109,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt,
> char *nodename)
> }
> #endif
>
> -#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max_, initfn) \
> - { \
> - .name = (type_name), \
> - .parent = TYPE_RISCV_DYNAMIC_CPU, \
> - .instance_init = (initfn), \
> - .class_data = (void*) &((const RISCVCPUDef) { \
> - .misa_mxl_max = (misa_mxl_max_), \
> - .priv_spec = RISCV_PROFILE_ATTR_UNUSED, \
> - .vext_spec = RISCV_PROFILE_ATTR_UNUSED, \
> - .cfg.max_satp_mode = -1, \
> - }), \
> - }
> -
> #define DEFINE_VENDOR_CPU(type_name, misa_mxl_max_, initfn) \
> { \
> .name = (type_name), \
> @@ -3241,7 +3165,12 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .class_base_init = riscv_cpu_class_base_init,
> },
>
> - DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_DYNAMIC_CPU, TYPE_RISCV_CPU),
> + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_DYNAMIC_CPU, TYPE_RISCV_CPU,
> + .cfg.mmu = true,
> + .cfg.pmp = true,
> + .priv_spec = PRIV_VERSION_LATEST,
> + ),
> +
> DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_VENDOR_CPU, TYPE_RISCV_CPU),
> DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_BARE_CPU, TYPE_RISCV_CPU,
> /*
> @@ -3269,15 +3198,23 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> #endif
> ),
>
> + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MAX, TYPE_RISCV_DYNAMIC_CPU,
> #if defined(TARGET_RISCV32)
> - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32,
> riscv_max_cpu_init),
> + .misa_mxl_max = MXL_RV32,
> + .cfg.max_satp_mode = VM_1_10_SV32,
> #elif defined(TARGET_RISCV64)
> - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64,
> riscv_max_cpu_init),
> + .misa_mxl_max = MXL_RV64,
> + .cfg.max_satp_mode = VM_1_10_SV57,
> #endif
> + ),
>
> #if defined(TARGET_RISCV32) || \
> (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
> - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, MXL_RV32,
> rv32_base_cpu_init),
> + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU,
> + .cfg.max_satp_mode = VM_1_10_SV32,
> + .misa_mxl_max = MXL_RV32,
> + ),
> +
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32,
> rv32_ibex_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32,
> rv32_sifive_e_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32,
> rv32_imafcu_nommu_cpu_init),
> @@ -3294,11 +3231,18 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> #endif
>
> #if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
> - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX32, MXL_RV32,
> riscv_max_cpu_init),
> + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MAX32, TYPE_RISCV_DYNAMIC_CPU,
> + .cfg.max_satp_mode = VM_1_10_SV32,
> + .misa_mxl_max = MXL_RV32,
> + ),
> #endif
>
> #if defined(TARGET_RISCV64)
> - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64,
> rv64_base_cpu_init),
> + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE64, TYPE_RISCV_DYNAMIC_CPU,
> + .cfg.max_satp_mode = VM_1_10_SV57,
> + .misa_mxl_max = MXL_RV64,
> + ),
> +
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64,
> rv64_sifive_e_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64,
> rv64_sifive_u_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64,
> rv64_sifive_u_cpu_init),
> @@ -3308,7 +3252,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
> MXL_RV64,
> rv64_xiangshan_nanhu_cpu_init),
> #ifdef CONFIG_TCG
> - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128,
> rv128_base_cpu_init),
> + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU,
> + .cfg.max_satp_mode = VM_1_10_SV57,
> + .misa_mxl_max = MXL_RV128,
> + ),
> #endif /* CONFIG_TCG */
> DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64I, TYPE_RISCV_BARE_CPU,
> .misa_mxl_max = MXL_RV64,
> --
> 2.49.0
>
