MSI interrupt is triggered by writing message on specified memory address.
In generic it is used by PCI devices, and no device is connected pch MSI
irqchip with GPIO pin line method, here remove gpio input setting for MSI
controller.
Signed-off-by: Bibo Mao <maob...@loongson.cn>
---
hw/intc/loongarch_pch_msi.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/hw/intc/loongarch_pch_msi.c b/hw/intc/loongarch_pch_msi.c
index 66b5c1e660..bc93504ff7 100644
--- a/hw/intc/loongarch_pch_msi.c
+++ b/hw/intc/loongarch_pch_msi.c
@@ -42,13 +42,6 @@ static const MemoryRegionOps loongarch_pch_msi_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void pch_msi_irq_handler(void *opaque, int irq, int level)
-{
- LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(opaque);
-
- qemu_set_irq(s->pch_msi_irq[irq], level);
-}
-
static void loongarch_pch_msi_realize(DeviceState *dev, Error **errp)
{
LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(dev);
@@ -59,9 +52,7 @@ static void loongarch_pch_msi_realize(DeviceState *dev, Error
**errp)
}
s->pch_msi_irq = g_new(qemu_irq, s->irq_num);
-
qdev_init_gpio_out(dev, s->pch_msi_irq, s->irq_num);
- qdev_init_gpio_in(dev, pch_msi_irq_handler, s->irq_num);
}
static void loongarch_pch_msi_unrealize(DeviceState *dev)
base-commit: 56c6e249b6988c1b6edc2dd34ebb0f1e570a1365
--
2.39.3
