On Fri, Mar 1, 2024 at 10:40 AM Peter Maydell <peter.mayd...@linaro.org>
wrote:
> On Wed, 28 Feb 2024 at 01:40, Gregory Anders <g...@gpanders.com> wrote:
> >
> > When the CPU is reset using PSS_RST_CTRL in the SLCR, bit 19 in
> > REBOOT_STATUS should be set.
> >
> Refer to page 1602 of the Xilinx Zynq 7000 Technical Reference Manual.
> >
> > Signed-off-by: Gregory Anders <g...@gpanders.com>
> > ---
> > hw/misc/zynq_slcr.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
> > index d2ac2e77f2..a8f1792bf6 100644
> > --- a/hw/misc/zynq_slcr.c
> > +++ b/hw/misc/zynq_slcr.c
> > @@ -120,6 +120,7 @@ REG32(RS_AWDT_CTRL, 0x24c)
> > REG32(RST_REASON, 0x250)
> >
> > REG32(REBOOT_STATUS, 0x258)
> > + FIELD(REBOOT_STATUS, SLC_RST, 19, 1)
> > REG32(BOOT_MODE, 0x25c)
> >
> > REG32(APU_CTRL, 0x300)
> > @@ -562,6 +563,7 @@ static void zynq_slcr_write(void *opaque, hwaddr
> offset,
> > switch (offset) {
> > case R_PSS_RST_CTRL:
> > if (FIELD_EX32(val, PSS_RST_CTRL, SOFT_RST)) {
> > + s->regs[R_REBOOT_STATUS] |= R_REBOOT_STATUS_SLC_RST_MASK;
> > qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> > }
> > break;
> > --
>
> The manual also says that "This field is written by ROM code",
> so as a model of the hardware should QEMU be writing it?
>
> I've cc'd the Zynq maintainers for their opinion.
>
>
Hi,
I don't have great answers unfortunately...
We haven't been super consistent with these things but on the ZynqMP we
sometimes require the user to apply ROM behaviour using -device loader on
the command-line (not great for this case since we wouldn't want the mask
to be set until a soft reset) or we conditionalize the ROM behaviour
checking if we're doing direct Linux boots..
Best regards,
Edgar
> thanks
> -- PMM
>
