> -----Original Message-----
> From: Zhao Liu <zhao1....@linux.intel.com>
> Sent: Tuesday, February 20, 2024 5:25 PM
> To: Daniel P . Berrangé <berra...@redhat.com>; Eduardo Habkost
> <edua...@habkost.net>; Marcel Apfelbaum
> <marcel.apfelb...@gmail.com>; Philippe Mathieu-Daudé <phi...@linaro.org>;
> Yanan Wang <wangyana...@huawei.com>;
> Michael S . Tsirkin <m...@redhat.com>; Paolo Bonzini <pbonz...@redhat.com>;
> Richard Henderson <richard.hender...@linaro.org>;
> Eric Blake <ebl...@redhat.com>; Markus Armbruster <arm...@redhat.com>;
> Marcelo Tosatti <mtosa...@redhat.com>; Alex Bennée
> <alex.ben...@linaro.org>; Peter Maydell <peter.mayd...@linaro.org>; Jonathan
> Cameron <jonathan.came...@huawei.com>;
> JeeHeng Sia <jeeheng....@starfivetech.com>
> Cc: qemu-devel@nongnu.org; k...@vger.kernel.org; qemu-ri...@nongnu.org;
> qemu-...@nongnu.org; Zhenyu Wang
> <zhenyu.z.w...@intel.com>; Dapeng Mi <dapeng1...@linux.intel.com>; Yongwei Ma
> <yongwei...@intel.com>; Zhao Liu
> <zhao1....@intel.com>
> Subject: [RFC 4/8] hw/core: Add cache topology options in -smp
>
> From: Zhao Liu <zhao1....@intel.com>
>
> Add "l1d-cache", "l1i-cache". "l2-cache", and "l3-cache" options in
> -smp to define the cache topology for SMP system.
>
> Signed-off-by: Zhao Liu <zhao1....@intel.com>
> ---
> hw/core/machine-smp.c | 128 ++++++++++++++++++++++++++++++++++++++++++
> hw/core/machine.c | 4 ++
> qapi/machine.json | 14 ++++-
> system/vl.c | 15 +++++
> 4 files changed, 160 insertions(+), 1 deletion(-)
>
> diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
> index 8a8296b0d05b..2cbd19f4aa57 100644
> --- a/hw/core/machine-smp.c
> +++ b/hw/core/machine-smp.c
> @@ -61,6 +61,132 @@ static char *cpu_hierarchy_to_string(MachineState *ms)
> return g_string_free(s, false);
> }
>
> +static bool machine_check_topo_support(MachineState *ms,
> + CPUTopoLevel topo)
> +{
> + MachineClass *mc = MACHINE_GET_CLASS(ms);
> +
> + if (topo == CPU_TOPO_LEVEL_MODULE && !mc->smp_props.modules_supported) {
> + return false;
> + }
> +
> + if (topo == CPU_TOPO_LEVEL_CLUSTER && !mc->smp_props.clusters_supported)
> {
> + return false;
> + }
> +
> + if (topo == CPU_TOPO_LEVEL_DIE && !mc->smp_props.dies_supported) {
> + return false;
> + }
> +
> + if (topo == CPU_TOPO_LEVEL_BOOK && !mc->smp_props.books_supported) {
> + return false;
> + }
> +
> + if (topo == CPU_TOPO_LEVEL_DRAWER && !mc->smp_props.drawers_supported) {
> + return false;
> + }
> +
> + return true;
> +}
> +
> +static int smp_cache_string_to_topology(MachineState *ms,
> + char *topo_str,
> + CPUTopoLevel *topo,
> + Error **errp)
> +{
> + *topo = string_to_cpu_topo(topo_str);
> +
> + if (*topo == CPU_TOPO_LEVEL_MAX || *topo == CPU_TOPO_LEVEL_INVALID) {
> + error_setg(errp, "Invalid cache topology level: %s. The cache "
> + "topology should match the CPU topology level", topo_str);
> + return -1;
> + }
> +
> + if (!machine_check_topo_support(ms, *topo)) {
> + error_setg(errp, "Invalid cache topology level: %s. The topology "
> + "level is not supported by this machine", topo_str);
> + return -1;
> + }
> +
> + return 0;
> +}
> +
> +static void machine_parse_smp_cache_config(MachineState *ms,
> + const SMPConfiguration *config,
> + Error **errp)
> +{
> + MachineClass *mc = MACHINE_GET_CLASS(ms);
> +
> + if (config->l1d_cache) {
> + if (!mc->smp_props.l1_separated_cache_supported) {
> + error_setg(errp, "L1 D-cache topology not "
> + "supported by this machine");
> + return;
> + }
> +
> + if (smp_cache_string_to_topology(ms, config->l1d_cache,
> + &ms->smp_cache.l1d, errp)) {
> + return;
> + }
> + }
> +
> + if (config->l1i_cache) {
> + if (!mc->smp_props.l1_separated_cache_supported) {
> + error_setg(errp, "L1 I-cache topology not "
> + "supported by this machine");
> + return;
> + }
> +
> + if (smp_cache_string_to_topology(ms, config->l1i_cache,
> + &ms->smp_cache.l1i, errp)) {
> + return;
> + }
> + }
> +
> + if (config->l2_cache) {
> + if (!mc->smp_props.l2_unified_cache_supported) {
> + error_setg(errp, "L2 cache topology not "
> + "supported by this machine");
> + return;
> + }
> +
> + if (smp_cache_string_to_topology(ms, config->l2_cache,
> + &ms->smp_cache.l2, errp)) {
> + return;
> + }
> +
> + if (ms->smp_cache.l1d > ms->smp_cache.l2 ||
> + ms->smp_cache.l1i > ms->smp_cache.l2) {
> + error_setg(errp, "Invalid L2 cache topology. "
> + "L2 cache topology level should not be "
> + "lower than L1 D-cache/L1 I-cache");
> + return;
> + }
> + }
> +
> + if (config->l3_cache) {
> + if (!mc->smp_props.l2_unified_cache_supported) {
> + error_setg(errp, "L3 cache topology not "
> + "supported by this machine");
> + return;
> + }
> +
> + if (smp_cache_string_to_topology(ms, config->l3_cache,
> + &ms->smp_cache.l3, errp)) {
> + return;
> + }
> +
> + if (ms->smp_cache.l1d > ms->smp_cache.l3 ||
> + ms->smp_cache.l1i > ms->smp_cache.l3 ||
> + ms->smp_cache.l2 > ms->smp_cache.l3) {
> + error_setg(errp, "Invalid L3 cache topology. "
> + "L3 cache topology level should not be "
> + "lower than L1 D-cache/L1 I-cache/L2 cache");
> + return;
> + }
> + }
> +}
> +
> /*
> * machine_parse_smp_config: Generic function used to parse the given
> * SMP configuration
> @@ -249,6 +375,8 @@ void machine_parse_smp_config(MachineState *ms,
> mc->name, mc->max_cpus);
> return;
> }
> +
> + machine_parse_smp_cache_config(ms, config, errp);
> }
>
> unsigned int machine_topo_get_cores_per_socket(const MachineState *ms)
> diff --git a/hw/core/machine.c b/hw/core/machine.c
> index 426f71770a84..cb5173927b0d 100644
> --- a/hw/core/machine.c
> +++ b/hw/core/machine.c
> @@ -886,6 +886,10 @@ static void machine_get_smp(Object *obj, Visitor *v,
> const char *name,
> .has_cores = true, .cores = ms->smp.cores,
> .has_threads = true, .threads = ms->smp.threads,
> .has_maxcpus = true, .maxcpus = ms->smp.max_cpus,
> + .l1d_cache = g_strdup(cpu_topo_to_string(ms->smp_cache.l1d)),
> + .l1i_cache = g_strdup(cpu_topo_to_string(ms->smp_cache.l1i)),
> + .l2_cache = g_strdup(cpu_topo_to_string(ms->smp_cache.l2)),
> + .l3_cache = g_strdup(cpu_topo_to_string(ms->smp_cache.l3)),
Let's standardize the code by adding the 'has_' prefix.
> };
>
> if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) {
> diff --git a/qapi/machine.json b/qapi/machine.json
> index d0e7f1f615f3..0a923ac38803 100644
> --- a/qapi/machine.json
> +++ b/qapi/machine.json
> @@ -1650,6 +1650,14 @@
> #
> # @threads: number of threads per core
> #
> +# @l1d-cache: topology hierarchy of L1 data cache (since 9.0)
> +#
> +# @l1i-cache: topology hierarchy of L1 instruction cache (since 9.0)
> +#
> +# @l2-cache: topology hierarchy of L2 unified cache (since 9.0)
> +#
> +# @l3-cache: topology hierarchy of L3 unified cache (since 9.0)
> +#
> # Since: 6.1
> ##
> { 'struct': 'SMPConfiguration', 'data': {
> @@ -1662,7 +1670,11 @@
> '*modules': 'int',
> '*cores': 'int',
> '*threads': 'int',
> - '*maxcpus': 'int' } }
> + '*maxcpus': 'int',
> + '*l1d-cache': 'str',
> + '*l1i-cache': 'str',
> + '*l2-cache': 'str',
> + '*l3-cache': 'str' } }
>
> ##
> # @x-query-irq:
> diff --git a/system/vl.c b/system/vl.c
> index a82555ae1558..ac95e5ddb656 100644
> --- a/system/vl.c
> +++ b/system/vl.c
> @@ -741,6 +741,9 @@ static QemuOptsList qemu_smp_opts = {
> }, {
> .name = "clusters",
> .type = QEMU_OPT_NUMBER,
> + }, {
> + .name = "modules",
> + .type = QEMU_OPT_NUMBER,
> }, {
> .name = "cores",
> .type = QEMU_OPT_NUMBER,
> @@ -750,6 +753,18 @@ static QemuOptsList qemu_smp_opts = {
> }, {
> .name = "maxcpus",
> .type = QEMU_OPT_NUMBER,
> + }, {
> + .name = "l1d-cache",
> + .type = QEMU_OPT_STRING,
> + }, {
> + .name = "l1i-cache",
> + .type = QEMU_OPT_STRING,
> + }, {
> + .name = "l2-cache",
> + .type = QEMU_OPT_STRING,
> + }, {
> + .name = "l3-cache",
> + .type = QEMU_OPT_STRING,
> },
> { /*End of list */ }
> },
> --
> 2.34.1
