> -----Original Message-----
> From: Zhao Liu <zhao1....@linux.intel.com>
> Sent: Tuesday, February 20, 2024 5:25 PM
> To: Daniel P . Berrangé <berra...@redhat.com>; Eduardo Habkost
> <edua...@habkost.net>; Marcel Apfelbaum
> <marcel.apfelb...@gmail.com>; Philippe Mathieu-Daudé <phi...@linaro.org>;
> Yanan Wang <wangyana...@huawei.com>;
> Michael S . Tsirkin <m...@redhat.com>; Paolo Bonzini <pbonz...@redhat.com>;
> Richard Henderson <richard.hender...@linaro.org>;
> Eric Blake <ebl...@redhat.com>; Markus Armbruster <arm...@redhat.com>;
> Marcelo Tosatti <mtosa...@redhat.com>; Alex Bennée
> <alex.ben...@linaro.org>; Peter Maydell <peter.mayd...@linaro.org>; Jonathan
> Cameron <jonathan.came...@huawei.com>;
> JeeHeng Sia <jeeheng....@starfivetech.com>
> Cc: qemu-devel@nongnu.org; k...@vger.kernel.org; qemu-ri...@nongnu.org;
> qemu-...@nongnu.org; Zhenyu Wang
> <zhenyu.z.w...@intel.com>; Dapeng Mi <dapeng1...@linux.intel.com>; Yongwei Ma
> <yongwei...@intel.com>; Zhao Liu
> <zhao1....@intel.com>
> Subject: [RFC 6/8] i386/cpu: Update cache topology with machine's
> configuration
>
> From: Zhao Liu <zhao1....@intel.com>
>
> User will configure SMP cache topology via -smp.
>
> For this case, update the x86 CPUs' cache topology with user's
> configuration in MachineState.
>
> Signed-off-by: Zhao Liu <zhao1....@intel.com>
> ---
> target/i386/cpu.c | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index d7cb0f1e49b4..4b5c551fe7f0 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -7582,6 +7582,27 @@ static void x86_cpu_realizefn(DeviceState *dev, Error
> **errp)
>
> #ifndef CONFIG_USER_ONLY
> MachineState *ms = MACHINE(qdev_get_machine());
> +
> + if (ms->smp_cache.l1d != CPU_TOPO_LEVEL_INVALID) {
> + env->cache_info_cpuid4.l1d_cache->share_level = ms->smp_cache.l1d;
> + env->cache_info_amd.l1d_cache->share_level = ms->smp_cache.l1d;
> + }
> +
> + if (ms->smp_cache.l1i != CPU_TOPO_LEVEL_INVALID) {
> + env->cache_info_cpuid4.l1i_cache->share_level = ms->smp_cache.l1i;
> + env->cache_info_amd.l1i_cache->share_level = ms->smp_cache.l1i;
> + }
> +
> + if (ms->smp_cache.l2 != CPU_TOPO_LEVEL_INVALID) {
> + env->cache_info_cpuid4.l2_cache->share_level = ms->smp_cache.l2;
> + env->cache_info_amd.l2_cache->share_level = ms->smp_cache.l2;
> + }
> +
> + if (ms->smp_cache.l3 != CPU_TOPO_LEVEL_INVALID) {
> + env->cache_info_cpuid4.l3_cache->share_level = ms->smp_cache.l3;
> + env->cache_info_amd.l3_cache->share_level = ms->smp_cache.l3;
> + }
> +
I think this block of code can be further optimized. Maybe we can create
a function called updateCacheShareLevel() that takes a cache pointer and
a share level as arguments. This function encapsulates the common
pattern of updating cache share levels for different caches. You can define
it like this:
void updateCacheShareLevel(XxxCacheInfo *cache, int shareLevel) {
if (shareLevel != CPU_TOPO_LEVEL_INVALID) {
cache->share_level = shareLevel;
}
}
> qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
>
> if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
> --
> 2.34.1
