On Saturday 19 August 2006 00:40, Igor Kovalenko wrote:
> Hi!
>
> This patch adds handling of multi-byte NOPs, recent gcc/gas uses them for
> x86 code padding.
> Patch checked with current opensuse-factory x86 guest installation which is
> built with new gcc/gas tools.
According to my amd64 documentation all of the opcodes 0f 19 through 0f 1f
should be implemented as a NOP. Also, I suspect the "invalid" prefetch ops
(0f 18) should also be implemented as nops.
The same implementation should be useable to all these opcodes.
Updated patch, extracted noop modrm processing into separate function and used it for 0f 18 case as well. I also removed reg sense from noop processing.
--
Kind Regards,
Igor V. Kovalenko
Index: target-i386/translate.c
===================================================================
RCS file: /cvsroot/qemu/qemu/target-i386/translate.c,v
retrieving revision 1.59
diff -u -r1.59 translate.c
--- target-i386/translate.c 10 Jul 2006 19:53:04 -0000 1.59
+++ target-i386/translate.c 20 Aug 2006 20:54:37 -0000
@@ -1615,6 +1615,43 @@
*offset_ptr = disp;
}
+static void gen_nop_modrm(DisasContext *s, int modrm)
+{
+ int rm, mod;
+ rm = modrm & 7;
+ mod = (modrm >> 6) & 3;
+
+ if (rm == 0x04)
+ {
+ /* SIB byte follows */
+ s->pc += 1;
+ }
+
+ switch (mod)
+ {
+ case 0x00:
+ if (rm == 0x05)
+ {
+ /* 32bit data follows */
+ s->pc += 4;
+ }
+ /* else register is specified */
+ break;
+ case 0x01:
+ /* 8bit data follows */
+ s->pc += 1;
+ break;
+ case 0x10:
+ /* 32bit data follows */
+ s->pc += 4;
+ break;
+ case 0x11:
+ default:
+ /* register is specified */
+ break;
+ }
+}
+
/* used for LEA and MOV AX, mem */
static void gen_add_A0_ds_seg(DisasContext *s)
{
@@ -5792,9 +5829,15 @@
/* nothing more to do */
break;
default:
- goto illegal_op;
+ gen_nop_modrm(s, modrm);
+ break;
}
break;
+ case 0x119 ... 0x11f:
+ /* multi-byte noop */
+ modrm = ldub_code(s->pc++);
+ gen_nop_modrm(s, modrm);
+ break;
case 0x120: /* mov reg, crN */
case 0x122: /* mov crN, reg */
if (s->cpl != 0) {
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