Hi,
The architecture used in sparc target (sun4m) supports SMP up to a maximum of 16 CPUs. At hardware emulation level (hw/*, target-sparc/*), it would be easy to add the missing interprocessor interrupts, per-CPU counters and atomic instructions. It would also be simple to add the prom functions for starting/stopping CPUs to Proll. Maybe some days' work in total.
Higher level (vl.c, cpu-exec.c) could need more work. Maybe Fabrice can enlighten us?
For some reason, Sparc performance is low (1/10 of native x86 nbench) compared to x86 (2/3). Simulating SMP on a uniprocessor would only decrease performance.
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