On Fri, Jan 24, 2025 at 10:05:04PM +0100, Hauke Mehrtens wrote:
> @Daniel: Is this PR fine about the rtl 2.5G PHY ready to merge or just a
> test?
> https://github.com/openwrt/openwrt/pull/17701

Well, it seems to resolve the issue, but I don't think it's the correct
fix.

Feel free to merge and backport, now that I've been stairing at that
issue for some time I think that we already got some other work-arounds
for what is probably the same issue under the hood:
 - 052732bddb generic: 6.6: fix early RTL8221B detection
 - 28b3a5e6b5 generic: net: phy: realtek: detect early version of RTL8221B

So this is basiacally the same issue:
The PHY (or the MDIO bus on those MediaTek SoCs?) not responding meaningful
values to (C22 and C45) reads for some time early during boot.
Increasing the PHY reset assert and deassert times also doesn't reliably
fix the issue; and why should the same PHY require 100x the specified
time after reset has been deasserted than it needs on other boards?!

And then the fact that swapping gmac0 and gmac1 in DT also fixes it, another
hint that we are dealing with something related to timing of the MDIO bus
driver rather than an issue related to the PHY itself.

Plus MediaTek got this rather odd patch in their SDK:

https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/refs/heads/master/autobuild/unified/global/24.10/files/target/linux/mediatek/patches-6.6/999-2700-net-ethernet-mtk_eth_soc-add-mdio-reset-delay.patch

(importing that to OpenWrt however doesn't fix the issue with RTL8221B)

All that being said, it's probably better to have that work-around than
having broken Ethernet on some but not all devices using RTL8221B-VB-CG...

@arinc9:
> 
> Currently we have the following known bugs:
> 
> [...]
>  * Ethernet link unstable on some mt7530 switches. Deactivate EEE
> (Energy-Efficient Ethernet) as a workaround, see:
> https://github.com/openwrt/openwrt/issues/17351

Any idea what could be going on there?


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