2014/1/3, danitool <dgcb...@gmail.com>: > I'm also having these problems. The bug is very easy to reproduce. Just > using the jffs2 image instead of squashfs, the problems are shown with the > first boot, and you can see lot of funny names just listing /etc/init.d > > root@(none):/# ls -l /etc/init.d/ > -rwxr-xr-x 1 root root 1993 Jan 2 2014 boot > -rwxr-xr-x 1 root root 368 Dec 20 2013 ciciixixmeme > -rwxr-xr-x 1 root root 729 Dec 20 2013 cron > -rwxr-xr-x 1 root root 3920 Jan 2 2014 dropbear > -rwxr-xr-x 1 root root 4173 Jan 2 2014 eleld?d > -rwxr-xr-x 1 root root 262 Jan 2 2014 firellll > -rwxr-xr-x 1 root root 2015 Dec 20 2013 led > -rwxr-xr-x 1 root root 926 Dec 20 2013 lnlnet > -rwxr-xr-x 1 root root 1694 Jan 2 2014 log > -rwxr-xr-x 1 root root 835 Dec 20 2013 lucihchcmimigrate > -rwxr-xr-x 1 root root 308 Dec 20 2013 nene > -rwxr-xr-x 1 root root 125 Dec 20 2013 scsctl > -rwxr-xr-x 1 root root 13640 Jan 2 2014 smsmq?q > -rwxr-xr-x 1 root root 718 Dec 20 2013 snsnd?d > -rwxr-xr-x 1 root root 945 Jan 2 2014 twtwk?k > -rwxr-xr-x 1 root root 3324 Jan 2 2014 uhttpd > -rwxr-xr-x 1 root root 106 Jan 2 2014 umount > -rwxr-xr-x 1 root root 522 Dec 20 2013 ununndnd > > It's like a baby learning to talk. > > Since this is happening when using a jffs2 image, overlayfs isn't used, > isn't it?, then the problem shouldn't be related to the overlayfs driver. > > I noticed another thing, probably not related to this, when I configure the > main thread to be the second core In CFE, openwrt gets stalled booting the > second core, I suppose the code lacks mechanisms to detect which core is up > and boot the other. > _______________________________________________ > openwrt-devel mailing list > openwrt-devel@lists.openwrt.org > https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel >
Thanks to the info collected by danitool and others (http://wiki.openwrt.org/doc/hardware/soc/soc.broadcom.bcm63xx/smp) and with the help of some code found in the Inventel Livebox source code could get some info about the cpu registers. This is the code with some additions: static void bmips_cpus_done(void) { int config; int introuting; int ctrl; config = read_c0_brcm_config_0(); if(!(config & BRCM_CONFIG0_CMT)) { printk("SMP not supported on this processor\n"); return; } else printk("SMP supported on this processor\n"); if(config & BRCM_CONFIG0_SIC) printk("Multicore CPU with split I-cache\n"); else printk("Multicore CPU with shared I-cache\n"); if(config & BRCM_CONFIG0_OWB) printk("Ordered Write Buffer enabled\n"); else printk("Ordered Write Buffer disabled\n"); if(config & BRCM_CONFIG0_BPD) printk("Branch prediction enabled\n"); else printk("Branch prediction disabled\n"); if(config & BRCM_CONFIG0_RAC) printk("RAC present\n"); else printk("RAC absent\n"); if(config & BRCM_CONFIG0_NBK) printk("NBK (non blocking Data Cache) enabled\n"); else printk("NBK (non blocking Data Cache) disabled\n"); introuting = read_c0_brcm_cmt_intr(); printk("Interrupt routing:\n"); if(introuting & CMT_INT_XIR_IP4) printk(" IP4: set A to T1, set B to T0\n"); else printk(" IP4: set A to T0, set B to T1\n"); if(introuting & CMT_INT_XIR_IP3) printk(" IP3: set A to T1, set B to T0\n"); else printk(" IP3: set A to T0, set B to T1\n"); if(introuting & CMT_INT_XIR_IP2) printk(" IP2: set A to T1, set B to T0\n"); else printk(" IP2: set A to T0, set B to T1\n"); if(introuting & CMT_INT_XIR_IP1) printk(" IP1: set A to T1, set B to T0\n"); else printk(" IP1: set A to T0, set B to T1\n"); if(introuting & CMT_INT_XIR_IP0) printk(" IP0: set A to T1, set B to T0\n"); else printk(" IP0: set A to T0, set B to T1\n"); if(introuting & CMT_INT_SIR_IP1) printk(" SOFT1: set A to T1, set B to T0\n"); else printk(" SOFT1: set A to T0, set B to T1\n"); if(introuting & CMT_INT_SIR_IP0) printk(" SOFT0: set A to T1, set B to T0\n"); else printk(" SOFT0: set A to T0, set B to T1\n"); if((introuting & CMT_INT_NMI_MASK) == 1) printk(" NMI routed to thread 0\n"); else printk(" NMI routed to thread 1\n"); ctrl = read_c0_brcm_cmt_ctrl(); printk("Control registers:\n"); if((ctrl & BRCM_CONFIG0_EP1) == 1) printk(" D-cache priority to thread 1\n"); else printk(" D-cache priority to thread ?\n"); printk(" No give exception priority to thread 1\n"); if((ctrl & BRCM_CONFIG0_EP0) == 1) printk(" D-cache priority to thread 0\n"); else printk(" D-cache priority to thread ?\n"); printk(" No give exception priority to thread 0\n"); } And here the bootlog: ....... [ 0.000000] Detected Broadcom 0x6368 CPU revision b2 ....... [ 0.048000] CPU revision is: 0002a031 (Broadcom BMIPS4350) [ 0.048000] Primary instruction cache 64kB, VIPT, 4-way, linesize 16 bytes. [ 0.048000] Primary data cache 32kB, 2-way, VIPT, cache aliases, linesize 16 bytes [ 0.076000] SMP: CPU1 is running [ 0.076000] Brought up 2 CPUs [ 0.076000] SMP supported on this processor [ 0.076000] Multicore CPU with split I-cache [ 0.076000] Ordered Write Buffer enabled [ 0.076000] Branch prediction disabled [ 0.076000] RAC present [ 0.076000] NBK (non blocking Data Cache) enabled [ 0.076000] Interrupt routing: [ 0.076000] IP4: set A to T0, set B to T1 [ 0.076000] IP3: set A to T0, set B to T1 [ 0.076000] IP2: set A to T0, set B to T1 [ 0.076000] IP1: set A to T1, set B to T0 [ 0.076000] IP0: set A to T0, set B to T1 [ 0.076000] SOFT1: set A to T1, set B to T0 [ 0.076000] SOFT0: set A to T1, set B to T0 [ 0.076000] NMI routed to thread 0 [ 0.076000] Control registers: [ 0.076000] D-cache priority to thread ? [ 0.076000] No give exception priority to thread 1 [ 0.076000] D-cache priority to thread ? [ 0.076000] No give exception priority to thread 0 ..... Called my attention that branch prediction is disabled, but surely there is a good reason to leave it in that state. Also noticed that SOFT1 and SOFT0 interrupts have the same configuration while in IP0 and IP1 are different. I haven't explored more registers because the wiki only defines some of them, but maybe is a good point to start digging deeper in this problem with jffs2 and BCM6368 (no idea if other Broadcom SMP capable SoCs have the same issue). Regards: José _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
