Hi David,
On 1/16/10, David Brownell <davi...@pacbell.net> wrote:
> On Saturday 16 January 2010, Alan Carvalho de Assis wrote:
>> I'm trying to figure out what DAP is waiting for.
>
> Sorry, cant help there. But surely turning on the debug
> output options (there's a separate JTAG I/O option too)
> should provide more than enough clues for you. :)
>
Thank you very much for these tips.
I changed the boot mode to internal boot, this way any code from
NAND/SD will be executed, then I got a little progress. See below.
Now I need to find a way to place the processor on halt mode. I tried
many commands, including "imx51.cpu arp_halt" with no success.
I'm reading the "CoreSight Technology System Design Guide", but there
is poor information about DAP.
Best Regards,
Alan
$ sudo openocd -f signalyzer.cfg -f imx51.cfg
Open On-Chip Debugger 0.4.0-rc1-dev-00043-g237a707 (2010-01-05-14:26)
For bug reports, read
http://openocd.berlios.de/doc/doxygen/bugs.html
2000 kHz
Warn : imx51.SDMA: nonstandard IR value
Info : device: 4 "2232C"
Info : deviceID: 67353760
Info : SerialNumber: 0100480 A
Info : Description: Signalyzer A
Info : clock speed 2000 kHz
Info : JTAG tap: imx51.DAP tap/device found: 0x1ba00477 (mfg: 0x23b,
part: 0xba00, ver: 0x1)
Info : TAP imx51.SDMA does not have IDCODE
Info : JTAG tap: imx51.SJC tap/device found: 0x1190c01d (mfg: 0x00e,
part: 0x190c, ver: 0x1)
Info : imx51.cpu: hardware has 1 breakpoints, 1 watchpoints
Info : accepting 'telnet' connection from 0
Info : JTAG tap: imx51.DAP tap/device found: 0x1ba00477 (mfg: 0x23b,
part: 0xba00, ver: 0x1)
Info : TAP imx51.SDMA does not have IDCODE
Info : JTAG tap: imx51.SJC tap/device found: 0x1190c01d (mfg: 0x00e,
part: 0x190c, ver: 0x1)
Error: imx51.cpu: how to reset?
Command handler execution failed
===== ARM registers
(0) r0 (/32)
(1) r1 (/32)
(2) r2 (/32)
(3) r3 (/32)
(4) r4 (/32)
(5) r5 (/32)
(6) r6 (/32)
(7) r7 (/32)
(8) r8 (/32)
(9) r9 (/32)
(10) r10 (/32)
(11) r11 (/32)
(12) r12 (/32)
(13) sp_usr (/32)
(14) lr_usr (/32)
(15) pc (/32)
(16) r8_fiq (/32)
(17) r9_fiq (/32)
(18) r10_fiq (/32)
(19) r11_fiq (/32)
(20) r12_fiq (/32)
(21) sp_fiq (/32)
(22) lr_fiq (/32)
(23) sp_irq (/32)
(24) lr_irq (/32)
(25) sp_svc (/32)
(26) lr_svc (/32)
(27) sp_abt (/32)
(28) lr_abt (/32)
(29) sp_und (/32)
(30) lr_und (/32)
(31) cpsr (/32)
(32) spsr_fiq (/32)
(33) spsr_irq (/32)
(34) spsr_svc (/32)
(35) spsr_abt (/32)
(36) spsr_und (/32)
(37) sp_mon (/32)
(38) lr_mon (/32)
(39) spsr_mon (/32)
Error: Target not halted
r0 (/32): 0x00000000
Error: Target not halted
r0 (/32): 0x00000000
a...@metropolis:~$ telnet 127.0.0.1 4444
Trying 127.0.0.1...
Connected to 127.0.0.1.
Escape character is '^]'.
Open On-Chip Debugger
> reset run
JTAG tap: imx51.DAP tap/device found: 0x1ba00477 (mfg: 0x23b, part:
0xba00, ver: 0x1)
TAP imx51.SDMA does not have IDCODE
JTAG tap: imx51.SJC tap/device found: 0x1190c01d (mfg: 0x00e, part:
0x190c, ver: 0x1)
imx51.cpu: how to reset?
Command handler execution failed
in procedure 'reset' called at file "command.c", line 638
called at file "command.c", line 352
> reg
===== ARM registers
(0) r0 (/32)
(1) r1 (/32)
(2) r2 (/32)
(3) r3 (/32)
(4) r4 (/32)
(5) r5 (/32)
(6) r6 (/32)
(7) r7 (/32)
(8) r8 (/32)
(9) r9 (/32)
(10) r10 (/32)
(11) r11 (/32)
(12) r12 (/32)
(13) sp_usr (/32)
(14) lr_usr (/32)
(15) pc (/32)
(16) r8_fiq (/32)
(17) r9_fiq (/32)
(18) r10_fiq (/32)
(19) r11_fiq (/32)
(20) r12_fiq (/32)
(21) sp_fiq (/32)
(22) lr_fiq (/32)
(23) sp_irq (/32)
(24) lr_irq (/32)
(25) sp_svc (/32)
(26) lr_svc (/32)
(27) sp_abt (/32)
(28) lr_abt (/32)
(29) sp_und (/32)
(30) lr_und (/32)
(31) cpsr (/32)
(32) spsr_fiq (/32)
(33) spsr_irq (/32)
(34) spsr_svc (/32)
(35) spsr_abt (/32)
(36) spsr_und (/32)
(37) sp_mon (/32)
(38) lr_mon (/32)
(39) spsr_mon (/32)
> reg r0
Target not halted
r0 (/32): 0x00000000
> reg r0 1
Target not halted
r0 (/32): 0x00000000
>
_______________________________________________
Openocd-development mailing list
Openocd-development@lists.berlios.de
https://lists.berlios.de/mailman/listinfo/openocd-development
