Hi David,
On 1/15/10, David Brownell <davi...@pacbell.net> wrote:
>> OpenOCD detects all TAPs, but I receive a Timeout:
>>
>> Warn : imx51.SDMA: nonstandard IR value
>> RCLK - adaptive
>> Info : device: 4 "2232C"
>> Info : deviceID: 67353760
>> Info : SerialNumber: 0100480 A
>> Info : Description: Signalyzer A
>> Info : RCLK (adaptive clock speed) not supported - fallback to 1000 kHz
>> Info : JTAG tap: imx51.DAP tap/device found: 0x1ba00477 (mfg: 0x23b, part:
>> 0xba00, ver: 0x1)
>> Info : TAP imx51.SDMA does not have IDCODE
>> Info : JTAG tap: imx51.SJC tap/device found: 0x0190c01d (mfg: 0x00e, part:
>> 0x190c, ver: 0x0)
>> Warn : failed to disable tap
>
> You don't have SJC-aware code to enable/disable the SDMA tap
> though, do you? What TAP were you trying to disable?
>
Really I based deeply on OMAP3530 config. BTW I think SDMA is bypassed
by default, as stated on MCIMX51RM.pdf 8.2.4:
"Supports the SDMA’s DR-path-only JTAG architecture by implementing
the controller portion of its TAP (including “BYPASS” as the default
state) within the SJC"
>
>> Warn : Timeout (1000ms) waiting for ACK=OK/FAULT (got ACK=0x1) in JTAG-DP
>> transaction
>> Warn : Timeout (1000ms) waiting for ACK=OK/FAULT (got ACK=0x1) in JTAG-DP
>> transaction
>> Warn : Timeout (1000ms) waiting for ACK=OK/FAULT (got ACK=0x1) in JTAG-DP
>> transaction
>> Warn : Timeout (1000ms) waiting for ACK=OK/FAULT (got ACK=0x1) in JTAG-DP
>> transaction
>
> That is, it's getting JTAG_ACK_WAIT not JTAG_ACK_OK_FAULT.
>
> Not clear what it's trying to do which is failing, but there's
> a bunch of strange stuff in your config which should be fixed.
> Such fixes might help.
>
I'm trying to figure out what DAP is waiting for.
>
>>
>> This is imx51.cfg for your reference:
>>
>> #--------------------------------------------------------------------------------------------------
>> # Freescale i.MX51
>>
>> if { [info exists CHIPNAME] } {
>> set _CHIPNAME $CHIPNAME
>> } else {
>> set _CHIPNAME imx51
>> }
>>
>> # CoreSight Debug Access Port
>> if { [info exists DAP_TAPID ] } {
>> set _DAP_TAPID $DAP_TAPID
>> } else {
>> set _DAP_TAPID 0x1ba00477
>> }
>>
>> jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \
>> -expected-id $_DAP_TAPID
>
> I'd drop the "-ircapture 0x1 -irmask 0xf" as being superfluous;
> those are the defaults.
>
Ok
>
>> # SDMA / no IDCODE
>> jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf
>
> In this case I'd drop just the "-irmask 0xf", to highlight that
> you're working around some JTAG oddity for that TAP.
>
>
Right
>
>> # SJC
>> if { [info exists SJC_TAPID ] } {
>> set _SJC_TAPID SJC_TAPID
>> } else {
>> set _SJC_TAPID 0x0190c01d
>> }
>>
>> jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
>> -expected-id $_SJC_TAPID
>
> Again I'd drop the "-ircapture 0x1 -irmask 0x1f", it's the default.
>
Ok
>
>> # GDB target: Cortex-A8, using DAP
>> set _TARGETNAME $_CHIPNAME.cpu
>> target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.DAP
>
> So far so good...
>
:-)
>
>> # some TCK tycles are required to activate the DEBUG power domain
>> jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
>>
>> # have the DAP "always" be active
>> jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
>
> Are you sure those two are correct? Looks like you did a cut/paste
> from the ICEpick support (OMAP3) ... but this chip has SJC not ICEpick.
>
I'm removed it and the "Warn : failed to disable tap" goes out.
> And I don't see any event code to *enable* the DAP using SJC, so there
> is no point in requesting that it be enabled. If it's not already
> present on the scan chain, you'd need to write SJC code to enable it.
>
Unfortunately Freescale removed "SJC guide" from final iMX51RM
documentation, I'm looking for it now.
> (And it would be a bit more correct, as I understand things, to label
> the SJC tap as "jrc" not "sjc". Yes it does a bit more than just
> switching the SDMA tap into or our of the scan chain, but so does
> ICEpick on TI parts.)
>
No, I think SJC (Secure JTAG Controller) is really different of JRC.
>
>> proc imx51_dbginit {target} {
>> # General Cortex A8 debug initialisation
>> cortex_a8 dbginit
>> }
>>
>> # Slow speed to be sure it will work
>> jtag_rclk 1000
>> $_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
>
> I take it the iMX51 is guaranteed to boot with at least an 8 MHz clock?
> Or whatever ... where did that "1 MHz" number come from?
>
I reduced this for safe detection, before I realize which SDMA was
disabled, I think SDMA core was running at least 1:8 as on i.MX31:
"The SDMA core has a design restriction of a 1:8 or greater ratio of
the TCK and SDMA core clocks. Thus for a 66 MHz SDMA core clock, the
TCK maximum frequency is limited to 8.25 MHz (= 66/8)."
>>
>> $_TARGETNAME configure -event reset-assert-post "imx51_dbginit
>> $_TARGETNAME"
>
> So far as I can tell, the OMAP3 should not need that "dbginit" thing,
> since it should be a side effect of the examine(). And you don't seem
> to have gotten to the point where you could tell if iMX51 needs it.
>
> So I'd disable that for now.
>
Ok, I did it, but still receiving same timeout message. Then I need to
find a way to active DAP correctly.
This is my current iMX51.cfg:
# Freescale i.MX51
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME imx51
}
# CoreSight Debug Access Port
if { [info exists DAP_TAPID ] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x1ba00477
}
jtag newtap $_CHIPNAME DAP -irlen 4 -expected-id $_DAP_TAPID
# SDMA / no IDCODE
jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0
# SJC
if { [info exists SJC_TAPID ] } {
set _SJC_TAPID SJC_TAPID
} else {
set _SJC_TAPID 0x0190c01d
}
jtag newtap $_CHIPNAME SJC -irlen 5 -expected-id $_SJC_TAPID
# GDB target: Cortex-A8, using DAP
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.DAP
Regards,
Alan
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