Hi! On Thu, Oct 1, 2009 at 9:41 PM, Magnus Lundin <lun...@mlu.mine.nu> wrote:
> Any ideas how OpenOCD should handle virtual addressing and cache coherency? > [..] > I am planning to implement these for the ARMv7A/CortexA8 and I am > interested in input on what you think should be the behaviour of these > functions in terms of VA/PA translations and cache coherency operations. > > I am not interested in designing a super complicated framework, rather I > would like some clear and reasonable simple rules when to use VA/PA > translation, when to clear caches and when to invalidate caches and how > this is mapped to user commands. > Any progress on it? I have a simple "works for me" implementation of memory access with cpu instead of AHB and virt2phys using cp15 for cortex_a8, but already got a problem with interfaces: there is only one set of functions on the high target level and if I switch them to mmu variants, I cannot enable debug on omap from tcl config, direct access is required there.
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