Any ideas how OpenOCD should handle virtual addressing and cache coherency?
Using the DAP MEMAP found on ARMv7 processors mean that we can write directly to memory mapped resources like RAM, FLASH, system control registers, debug registers and I/O control registers. This access can be done in in some cases must be done with the processor core running. For these target we can also use the processor core to access memory mapped resources, then we can get "automatic" MMU VA/PA mapping and at least d-cache handling. We also have different usage scenarios like writing to flash, uploading programs or data to RAM with or without MMU active, debugging standaone code or the Linux kernel. All of these resorces and debug scenarios need different handling of whether to use virtual adresses or physical addresses, when to invalidate caches and when to clean caches. For user control at the moment we have mdw/mww memory access and for some targets (arm720t, arm920t, arm926ejs) also mdw_phys, mww_phys and virt2phys translation functions. I am planning to implement these for the ARMv7A/CortexA8 and I am interested in input on what you think should be the behaviour of these functions in terms of VA/PA translations and cache coherency operations. I am not interested in designing a super complicated framework, rather I would like some clear and reasonable simple rules when to use VA/PA translation, when to clear caches and when to invalidate caches and how this is mapped to user commands. Best regards, Magnus _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
