Magnus Lundin wrote:
David Brownell wrote:
I think that's not quite following the model which the code in
the src/helper/startup.tcl file is expecting ... a closer match
would use reset-assert-pre (or maybe "post") not reset-start.
I have done some more testing and trying to understand the reset
handling in OpenOCD.
This is my understanding of the sequence
-------------
reset-start
jtag-reset
Here the omap3.dap tap is marked as disabled
reset-assert-pre
target reset assert
This is only called if the tap is enabled
For CortexA8 we want to set target state to reset and invalidate all
cached registers
reset assert post
reset-deassert-pre
target reset deassert
This is only called if the tap is enabled
For CortexA8 we want to halt the target for reset halt, this needs
the tap to be enabled
reset deassert post
reset end
------------------
My interpretation is:
We must write the reset command to PRM_RSTCTRL before the jtag reset stuff.
Otherwise the tap will be marked as disabled, even if is still
enabled, since the reset has not yet happened, and the mww is impossible.
( It actually kills OpenOCD with
openocd: driver.c:243: interface_jtag_add_dr_scan: Assertion `field ==
out_fields + scan->num_fields' failed. )
The omap3_debugint must be called after the jtag reset stuff and before
target reset assert
Otherwise the CortexA8 reset assert will not be called since the tap is
disabled
This gives the following reset event configurationb:
omap3.cpu configure -event reset-start "omap3.cpu mww $PRM_RSTCTRL 2"
omap3.cpu configure -event reset-assert-pre "omap3_dbginit"
I updated and tested your patch with this (see attachment), seems to work.
Cheers
Dirk
Index: a/tcl/target/omap3530.cfg
===================================================================
--- a/tcl/target/omap3530.cfg (revision 2768)
+++ b/tcl/target/omap3530.cfg (working copy)
@@ -42,7 +42,6 @@
# FIXME much of this should be in reset event handlers
proc omap3_dbginit { } {
poll off
- reset
sleep 100
jtag tapenable omap3530.dap
@@ -54,3 +53,17 @@
poll on
}
+set PRM_RSTCTRL 0x48307250
+
+proc omap3_reset { } {
+ # Global software reset
+ # RST_GS bit in PRM_RSTCTRL
+ mww $PRM_RSTCTRL 2
+ omap3_dbginit
+ halt
+}
+
+omap3.cpu configure -event reset-start "omap3.cpu mww $PRM_RSTCTRL 2"
+omap3.cpu configure -event reset-assert-pre "omap3_dbginit"
+
+
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