There is one more problem with reset handling during init. for ft2232
chips [at least on Olimex dongle].

When you first plug-in the Olimex dongle to USB port it drives srst
signal low. This cause failure (see output below) during initial openocd
JTAG scan. It only fails on the first try. All later attempts work fine.

This is of course with libftdi library. There are two solutions to this
problem. 
1. put reset_on_init patch that I submitted earlier and make it
dependent on hardware used to access JTAG.
2. put in udev rules a small program that will de-assert srst. I am not
sure if would be committed to openocd tree?

Comments or ideas?



Open On-Chip Debugger 0.3.0-in-development (2009-09-29-10:18) svn:2771
$URL: svn://svn.berlios.de/openocd/trunk/src/openocd.c $
For bug reports, read
http://svn.berlios.de/svnroot/repos/openocd/trunk/BUGS
100 kHz
jtag_nsrst_assert_width: 100
jtag_ntrst_assert_width: 100
jtag_nsrst_delay: 100
jtag_ntrst_delay: 100
Info : Disabled memory write burst mode.
Info : clock speed 100 kHz
Error: JTAG scan chain interrogation failed: all zeroes
Error: Check JTAG interface, timings, target power, etc.
Error: Trying to use configured scan chain anyway...
Error: c100.dsp: IR capture error; saw 0x0000 not 0x..1
Warn : Errors during IR capture, continuing anyway...
Error: 'arm11 target' JTAG communication error SCREG SCAN OUT 0x00
(expected 0x10)


Open On-Chip Debugger 0.3.0-in-development (2009-09-29-10:18) svn:2771
$URL: svn://svn.berlios.de/openocd/trunk/src/openocd.c $
For bug reports, read
http://svn.berlios.de/svnroot/repos/openocd/trunk/BUGS
100 kHz
jtag_nsrst_assert_width: 100
jtag_ntrst_assert_width: 100
jtag_nsrst_delay: 100
jtag_ntrst_delay: 100
Info : Disabled memory write burst mode.
Info : clock speed 100 kHz
Info : JTAG tap: c100.dsp tap/device found: 0x27b3645b (mfg: 0x22d,
part: 0x7b36, ver: 0x2)
Info : JTAG tap: c100.cpu tap/device found: 0x27b3645b (mfg: 0x22d,
part: 0x7b36, ver: 0x2)
Info : found ARM1136
^C


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