I understand that you do not want to make any changes so close to the
release of a new version. No problem. I made 3 changes in the table amt_jtagaccel_tap_move. This table defines how to move from one state to the other. It consists of two bytes per state move. The five LSB of the first byte will be shifted out to the right to the TMS-line. If you need an other 5 bytes to reach the desired state, you have to OR the first word with 0x80 and supply the next 5 bits in the second word (5 LSB). The first change is the neccesary one to correct the problem. This is the sequence to go from state RESET to state DRSHIFT. The value of these 2 bytes were 0x8a and 0x04. This means that the bitstream to do this transition is 0b 00100 01010 (send LSB first). This will bring you from the reset state to the shift state, but you enter the shift-state twice, which explains why the ID-CODE that will be read next is already shifted 1 bit. I corrected this to 0x05 and 0x00. This will send te bitstream 0b00101 (send LSB first). This will bring you from the RESET state to the DRSHIFT state more directly and without entering the DRSHIFT state twice. After checking the whole table, I found two other transitions that were correct, but could be optimized (5 bits in stead of 10 bits). Summary off all changes: From To Old values Old Bitstream New values New Bitstream Remark ---- ------- ---------- ------------- ---------- ------------- ------ RESET DRSHIFT 0x8a 0x04 0b00100 01010 0x05 0x00 0b00101 To Correct the error (and optimization) IDLE DRSHIFT 0x85 0x08 0b01000 00101 0x04 0x00 0b00100 Optimization IDLE IRSHIFT 0x8b 0x08 0b01000 01011 0x06 0x00 0b00110 Optimization Hopefully, this explanation helps. Good luck with your 0.2.0 branch release! P.S. I'm working on the code of the amt_jtagaccel interface to incorporate speed setting in kHz. Ferdinand Postema Zach Welch schreef: Without further confirmation of this patch's correctness, I do not want to add it until after the 0.2.0 branch release. I have been trying to push that out for most of the week, but it would be good to include this fix if it is indeed required.Can you perhaps provide a little more explanation regarding why you believe this patch to be correct? Sorry for having to ask, but I need to learn the details in order to make an informed decision about it. On Fri, 2009-07-03 at 22:16 +0200, Ferdinand Postema wrote:Hello, I found the bug by myself. I have made a patch file to correct it. Is it possible to incorporate this patch into the source code? Ferdinand Postema Ferdinand Postema schreef:First I want to say that I am very happy with the OpenOCD-software! I like it very much. I have a Chameleon POD from Amontec. This dongle can be programmed to act as a Wiggler-cable, but also as a JTAG Accelerator interface. I use it in combination with an ARM processor and a FPGA. Both are supplied by Propox. When I use the Wiggler JTAG interface, I get the following information: Info : JTAG tap: at91sam9260.cpu tap/device found: 0x0792603f (Manufacturer: 0x01f, Part: 0x7926, Version: 0x0) When I use the Amontec JTAG Accelerator Interface, I get the following information: Info : JTAG tap: at91sam9260.cpu tap/device found: 0x03c9301f (Manufacturer: 0x00f, Part: 0x3c93, Version: 0x0) It looks like the whole word is shifted 1 bit. I think the Wiggler interface is correct. I also tried my FPGA module and got the following ID's: Manuf. Chip wiggler amtjtagaccel Processor: Atmel AT91SAM9260 0x0792603f 0x03c9301f Platform Flash: Xilinx XCF01S 0xF5044093 0x7A822049 FPGA: Xilinx XC3S200 0x01414093 0x80A0A049 The ID of the FPGA is not only shifted 1 bit to the right, but is also OR-ed with 0x80000000 The wiggler ID is correct Can you correct this? Kind regards, Ferdinand Postema (The Netherlands)plain text document attachment (openocd_wrong_id_code.patch) Index: src/jtag/amt_jtagaccel.c =================================================================== --- src/jtag/amt_jtagaccel.c (revision 2461) +++ src/jtag/amt_jtagaccel.c (working copy) @@ -92,8 +92,8 @@ static uint8_t amt_jtagaccel_tap_move[6][6][2] = { /* RESET IDLE DRSHIFT DRPAUSE IRSHIFT IRPAUSE */ - {{0x1f, 0x00}, {0x0f, 0x00}, {0x8a, 0x04}, {0x0a, 0x00}, {0x06, 0x00}, {0x96, 0x00}}, /* RESET */ - {{0x1f, 0x00}, {0x00, 0x00}, {0x85, 0x08}, {0x05, 0x00}, {0x8b, 0x08}, {0x0b, 0x00}}, /* IDLE */ + {{0x1f, 0x00}, {0x0f, 0x00}, {0x05, 0x00}, {0x0a, 0x00}, {0x06, 0x00}, {0x96, 0x00}}, /* RESET */ + {{0x1f, 0x00}, {0x00, 0x00}, {0x04, 0x00}, {0x05, 0x00}, {0x06, 0x00}, {0x0b, 0x00}}, /* IDLE */ {{0x1f, 0x00}, {0x0d, 0x00}, {0x00, 0x00}, {0x01, 0x00}, {0x8f, 0x09}, {0x8f, 0x01}}, /* DRSHIFT */ {{0x1f, 0x00}, {0x0c, 0x00}, {0x08, 0x00}, {0x00, 0x00}, {0x8f, 0x09}, {0x8f, 0x01}}, /* DRPAUSE */ {{0x1f, 0x00}, {0x0d, 0x00}, {0x07, 0x00}, {0x97, 0x00}, {0x00, 0x00}, {0x01, 0x00}}, /* IRSHIFT */ _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development |
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