(I saw Duane is following up on this one and he's pretty much the expert on it...)
> If I've got an FPGA *not* programmed with a Nios core, > that model doesn't work. :) > > That issue isn't entirely "reset". It's "initialization", > which is a separable chunk of reset processing. For a > Nios core you could have "system reset" requiring both > "FPGA init" loading the core, and then "core reset". > But other FPGA bitstreams might not have a target. I'd like to be able to fire up a GDB debug session without having to worry about first configuring the FPGA. E.g. there might be default parameters set in the FPGA that resetting the Nios core does not reset, so I may very well want to reconfigure the FPGA upon each GDB session. On rewriting the reset routine: if we have 1000 targets that can be handled via parameters & events, then I'm OK with having one weird target rewrite the reset tcl proc. It's just an option available to targets that would unnecessarily complicate the more common targets. On adding options/events, then open source target support :-) is the ultimate configuration power/flexibility, we can add new options/events or change the default tcl reset proc as needed. -- Øyvind Harboe Embedded software and hardware consulting services http://www.zylin.com _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
