Magnus Lundin wrote: > tangray wrote: >> Hi all, >> >> I could not enter debug state when I set DRCR[0] to "b1", And I get the >> DSCR[1:0] value is "b10" >> any idea? >> >> >> DRCR:Debug Run Control Register >> >> DSCR:Debug Status and Control Register >> >> these registers is on page 12.4.12 of Cortex-A8 TRM >> >> > The problem is that DBGEN signal must be high, this is external to the > Cortex-A8 . For OMAP3530 this is controlled from bit 13 in > 0x5401d030, this found in the OMAP35xx 25.6.4. > > mww 0x5401d030 0x00002026 > > Then I can actually halt and restart the processor, i run only U-Boot > and sometimes it crashes and wont but we have halting debug.
This sounds great! I wonder if it makes sense to add the current state to OpenOCD code and what will be needed for this? I.e. does it already make sense to add code to OpenOCD (cortex_a8.c?) to be able to connect to OpenOCD by gdb and to stop/run the target via gdb? This would mean that we move the code we actually have in TCL script // version jtag tapenable omap3.cpu target create omap3.cpu cortex_a8 -endian little -chain-position omap3.cpu // targets sleep 1000 dap apsel 1 sleep 1000 dap apsel 1 // dap info 1 omap3.cpu mww 0x54011FB0 0xC5ACCE55 4 omap3.cpu mdw 0x54011314 omap3.cpu mdw 0x54011314 // omap3.cpu mdw 0x54011080 4 omap3.cpu mww 0x5401d030 0x00002026 in target support? What will be needed for this? Best regards Dirk _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
