tangray wrote: > Hi all, > > I could not enter debug state when I set DRCR[0] to "b1", And I get the > DSCR[1:0] value is "b10" > any idea? > > > DRCR:Debug Run Control Register > > DSCR:Debug Status and Control Register > > these registers is on page 12.4.12 of Cortex-A8 TRM > > The problem is that DBGEN signal must be high, this is external to the Cortex-A8 . For OMAP3530 this is controlled from bit 13 in 0x5401d030, this found in the OMAP35xx 25.6.4.
mww 0x5401d030 0x00002026 Then I can actually halt and restart the processor, i run only U-Boot and sometimes it crashes and wont but we have halting debug. Regards Magnus _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
