On Wed, 2009-04-22 at 14:31 -0500, Dick Hollenbeck wrote: > Zach Welch wrote: > > On Wed, 2009-04-22 at 11:07 -0700, Rick Altherr wrote: > > [snip] > > > >> This is an interesting idea, but I think it skips an important step. > >> There seem to be a number of problems solely within the JTAG and > >> interface layers. It would be great if someone constructed some > >> infrastructure for a regression suite that looked at just those > >> layers. That way we could verify those layers are functioning > >> properly across the board and do so in a way where people with the > >> correct equipment could quickly run the test periodically. > >> > > > > I don't know why I forgot it myself, but a test suite is now on The List > > with numerous bullets beneath it. > > > > > Yes, this is an FPGA with a serial port on it? The is your universal > JTAG TAP emulator, which gives feedback about the path than an actual > TAP is traversing. > > Without a device to connect to, one that gives responses back, how do > you verify success?
Functional unit testing could be a start. We could exercise a ton of code without ever needing to talk to the hardware. That was what I was thinking when I added the items to The List. A device like you describe could definitely be used for deeper testing, and it's not a particularly bad idea. I have been meaning to get into synthesizing my own FPGAs, and this sounds like a fairly easy and useful starter project. It is now on The List as well, unless you are now going to tell me why my child-like ignorance has led me astray. You may have well just tempted me with Pandora's box. I must know more. Cheers, Zach _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
