Spencer Oliver wrote: >> This works with a configured 72 MHz clock on the target, >> in my case from the preprogrammed board test application. >> >> The performance of the target flash controller is now the main >> limiting factor. >> >> > > I would commit this aswell, this could also be applied to the arm4_5 target. > > Currently we save/restore the registers after every algorithm run - during a > flash write this could mean multiple runs to complete. I would like to > change the scheme so that we save at the start of a flash algorithm and > restore when programming is fully complete. > > Cheers > Spen > Saving the registers is automatic when the algorithm halts (debug_entry code) and I dont want to mess with that unnecessarily.
Alternatively we use some communications while the algorithm is running to download the next block, dcc communications or for Cortex-M3 we can write directly to RAM while the algoritm is processing the first block. The slight problem with this is that download speed (jtag_khz) must be decreased to avoid overruns due to both target cpu and swjdp accessing RAM at the same time. For this we need the separation of run_algorithm into two phases with inner phase (run_it) dependent of the operation that armv4_5 uses. Regards Magnus _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
