Hello.
On 01/27/2016 04:49 AM, Simon Horman wrote:
From: Kazuya Mizuguchi <kazuya.mizuguchi...@renesas.com>
Kaneko-san, with the amount of the review changes, it might make sense for
you to assume the authorship of this patch, only noting it's based on
Mizuguchi-san's work. In principle, when you change the original patch, you
should document the changes you made in the change log, above ---...
This patch supports the following interrupts.
- One interrupt for multiple (descriptor, error, management)
- One interrupt for emac
- Four interrupts for dma queue (best effort rx/tx, network control rx/tx)
This patch improve efficiency of the interrupt handler by adding the
interrupt handler corresponding to each interrupt source described
above. Additionally, it reduces the number of times of the access to
EthernetAVB IF.
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi...@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
I have tested this patch and the result seems positive.
Tested on gen3 only I guess?
Yes, that is correct.
Please let me know if any more/different testing would help.
Sanity testing on some gen2 SoC wouldn't hurt (if you have time).
I don't believe that I have access to a gen2 board (+ extra hardware ?)
where ravb works.
Sorry, I just forgot about that.
If you do would it be possible for you to do a sanity test?
Yes, of course.
MBR, Sergei
