pon., 11 sty 2021 o 14:54 Bjarni Jonasson <bjarni.jonas...@microchip.com> napisał(a): > Sparx-5 supports this mode and it is missing in the PHY core. > > Signed-off-by: Bjarni Jonasson <bjarni.jonas...@microchip.com> > --- > include/linux/phy.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/include/linux/phy.h b/include/linux/phy.h > index 56563e5e0dc7..dce867222d58 100644 > --- a/include/linux/phy.h > +++ b/include/linux/phy.h > @@ -111,6 +111,7 @@ extern const int phy_10gbit_features_array[1]; > * @PHY_INTERFACE_MODE_10GBASER: 10G BaseR > * @PHY_INTERFACE_MODE_USXGMII: Universal Serial 10GE MII > * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN > + * @PHY_INTERFACE_MODE_100BASEX: 100 BaseX > * @PHY_INTERFACE_MODE_MAX: Book keeping [...]
This is kernel-internal interface, so maybe the new mode can be inserted before 1000baseX for easier lookup? Best Regards Michał Mirosław
