This change is required by the later patches.
Cc: Ben Widawsky <b...@bwidawsk.net>
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 3 ++-
src/mesa/drivers/dri/i965/brw_misc_state.c | 8 +++++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 ++-----
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +-
4 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index eac1f00..cb5ef58 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -144,7 +144,8 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t
*tile_x,
{
uint32_t mask_x, mask_y;
- intel_miptree_get_tile_masks(mt, &mask_x, &mask_y, map_stencil_as_y_tiled);
+ intel_miptree_get_tile_masks(mt->tiling, mt->cpp, &mask_x, &mask_y,
+ map_stencil_as_y_tiled);
*tile_x = x_offset & mask_x;
*tile_y = y_offset & mask_y;
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index e9d9467..246aefb 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -174,11 +174,13 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt,
uint32_t tile_mask_x = 0, tile_mask_y = 0;
if (depth_mt) {
- intel_miptree_get_tile_masks(depth_mt, &tile_mask_x, &tile_mask_y,
false);
+ intel_miptree_get_tile_masks(depth_mt->tiling, depth_mt->cpp,
+ &tile_mask_x, &tile_mask_y, false);
if (intel_miptree_level_has_hiz(depth_mt, depth_level)) {
uint32_t hiz_tile_mask_x, hiz_tile_mask_y;
- intel_miptree_get_tile_masks(depth_mt->hiz_buf->mt,
+ intel_miptree_get_tile_masks(depth_mt->hiz_buf->mt->tiling,
+ depth_mt->hiz_buf->mt->cpp,
&hiz_tile_mask_x, &hiz_tile_mask_y,
false);
@@ -200,7 +202,7 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt,
tile_mask_y |= 63;
} else {
uint32_t stencil_tile_mask_x, stencil_tile_mask_y;
- intel_miptree_get_tile_masks(stencil_mt,
+ intel_miptree_get_tile_masks(stencil_mt->tiling, stencil_mt->cpp,
&stencil_tile_mask_x,
&stencil_tile_mask_y, false);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index e85c3f0..b4f2bd8 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1087,13 +1087,10 @@ intel_miptree_get_image_offset(const struct
intel_mipmap_tree *mt,
* untiled, the masks are set to 0.
*/
void
-intel_miptree_get_tile_masks(const struct intel_mipmap_tree *mt,
+intel_miptree_get_tile_masks(uint32_t tiling, uint32_t cpp,
uint32_t *mask_x, uint32_t *mask_y,
bool map_stencil_as_y_tiled)
{
- int cpp = mt->cpp;
- uint32_t tiling = mt->tiling;
-
if (map_stencil_as_y_tiled)
tiling = I915_TILING_Y;
@@ -1176,7 +1173,7 @@ intel_miptree_get_tile_offsets(const struct
intel_mipmap_tree *mt,
uint32_t x, y;
uint32_t mask_x, mask_y;
- intel_miptree_get_tile_masks(mt, &mask_x, &mask_y, false);
+ intel_miptree_get_tile_masks(mt->tiling, mt->cpp, &mask_x, &mask_y, false);
intel_miptree_get_image_offset(mt, level, slice, &x, &y);
*tile_x = x & mask_x;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 790d312..b1617a2 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -622,7 +622,7 @@ intel_miptree_get_dimensions_for_image(struct
gl_texture_image *image,
int *width, int *height, int *depth);
void
-intel_miptree_get_tile_masks(const struct intel_mipmap_tree *mt,
+intel_miptree_get_tile_masks(uint32_t tiling, uint32_t cpp,
uint32_t *mask_x, uint32_t *mask_y,
bool map_stencil_as_y_tiled);
--
2.4.3
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