On Fri, Aug 14, 2015 at 04:51:53PM -0700, Anuj Phogat wrote:
> A later patch in this series uses it to compute tile dimensions.
>
> Cc: Ben Widawsky <b...@bwidawsk.net>
> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
> ---
> src/mesa/drivers/dri/i965/brw_blorp.cpp | 3 ++-
> src/mesa/drivers/dri/i965/brw_misc_state.c | 10 ++++---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 39
> ++++++++++++++++++++++++---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +-
> 4 files changed, 45 insertions(+), 9 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
> b/src/mesa/drivers/dri/i965/brw_blorp.cpp
> index cb5ef58..9195514 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
> @@ -144,7 +144,8 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t
> *tile_x,
> {
> uint32_t mask_x, mask_y;
>
> - intel_miptree_get_tile_masks(mt->tiling, mt->cpp, &mask_x, &mask_y,
> + intel_miptree_get_tile_masks(mt->tiling, mt->tr_mode, mt->cpp,
> + &mask_x, &mask_y,
> map_stencil_as_y_tiled);
>
> *tile_x = x_offset & mask_x;
> diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
> b/src/mesa/drivers/dri/i965/brw_misc_state.c
> index 246aefb..62bb1e3 100644
> --- a/src/mesa/drivers/dri/i965/brw_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
> @@ -174,12 +174,14 @@ brw_get_depthstencil_tile_masks(struct
> intel_mipmap_tree *depth_mt,
> uint32_t tile_mask_x = 0, tile_mask_y = 0;
>
> if (depth_mt) {
> - intel_miptree_get_tile_masks(depth_mt->tiling, depth_mt->cpp,
> - &tile_mask_x, &tile_mask_y, false);
> + intel_miptree_get_tile_masks(depth_mt->tiling, depth_mt->tr_mode,
> + depth_mt->cpp, &tile_mask_x, &tile_mask_y,
> + false);
>
> if (intel_miptree_level_has_hiz(depth_mt, depth_level)) {
> uint32_t hiz_tile_mask_x, hiz_tile_mask_y;
> intel_miptree_get_tile_masks(depth_mt->hiz_buf->mt->tiling,
> + depth_mt->hiz_buf->mt->tr_mode,
> depth_mt->hiz_buf->mt->cpp,
> &hiz_tile_mask_x, &hiz_tile_mask_y,
> false);
> @@ -202,7 +204,9 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
> *depth_mt,
> tile_mask_y |= 63;
> } else {
> uint32_t stencil_tile_mask_x, stencil_tile_mask_y;
> - intel_miptree_get_tile_masks(stencil_mt->tiling, stencil_mt->cpp,
> + intel_miptree_get_tile_masks(stencil_mt->tiling,
> + stencil_mt->tr_mode,
> + stencil_mt->cpp,
> &stencil_tile_mask_x,
> &stencil_tile_mask_y, false);
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index b4f2bd8..55dc80d 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -1087,7 +1087,7 @@ intel_miptree_get_image_offset(const struct
> intel_mipmap_tree *mt,
> * untiled, the masks are set to 0.
> */
> void
> -intel_miptree_get_tile_masks(uint32_t tiling, uint32_t cpp,
> +intel_miptree_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
> uint32_t *mask_x, uint32_t *mask_y,
> bool map_stencil_as_y_tiled)
> {
> @@ -1105,8 +1105,38 @@ intel_miptree_get_tile_masks(uint32_t tiling, uint32_t
> cpp,
> *mask_y = 7;
> break;
> case I915_TILING_Y:
> - *mask_x = 128 / cpp - 1;
> - *mask_y = 31;
> + if (tr_mode == INTEL_MIPTREE_TRMODE_NONE)
> + {
extra newline
> + *mask_x = 128 / cpp - 1;
> + *mask_y = 31;
> + } else {
> + uint32_t aspect_ratio = 1;
> + switch (cpp) {
> + case 1:
> + *mask_y = 64;
> + break;
> + case 2:
> + aspect_ratio = 2;
> + /* fallthrough */
> + case 4:
> + *mask_y = 32;
> + break;
> + case 8:
> + aspect_ratio = 2;
> + /* fallthrough */
> + case 16:
> + *mask_y = 16;
> + break;
> + default:
> + unreachable("not reached");
> + }
> +
I think it is a bit easier to read if you pull the aspect ratio out into a
separate statement (entirely up to you):
uint32_t aspect_ratio = 1;
switch (cpp) {
case 1:
*mask_y = 64;
break;
case 2:
case 4:
*mask_y = 32;
break;
case 8:
case 16:
*mask_y = 16;
break;
default:
unreachable("not reached");
}
if (cpp == 2 || cpp == 8)
aspect_ratio = 2;
Actually you begin to notice that powers of 4 have aspect ratio 1, and the rest
2 - but I think the switch statement is a nicer way to represent this - fwiw
it's something like (I didn't actually compile...):
*mask_x = 64 / (ALIGN(ffs(cpp) - 1, 2) ?: 1));
aspect_ratio = (ffs(cpp) - 1) % 2 ? 2 : 1;
> + if (tr_mode == INTEL_MIPTREE_TRMODE_YS)
> + *mask_y *= 4;
> +
> + *mask_x = *mask_y * aspect_ratio - 1;
> + *mask_y -= 1;
> + }
> break;
> }
> }
> @@ -1173,7 +1203,8 @@ intel_miptree_get_tile_offsets(const struct
> intel_mipmap_tree *mt,
> uint32_t x, y;
> uint32_t mask_x, mask_y;
>
> - intel_miptree_get_tile_masks(mt->tiling, mt->cpp, &mask_x, &mask_y,
> false);
> + intel_miptree_get_tile_masks(mt->tiling, mt->tr_mode, mt->cpp,
> + &mask_x, &mask_y, false);
> intel_miptree_get_image_offset(mt, level, slice, &x, &y);
>
> *tile_x = x & mask_x;
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> index b1617a2..fc68146 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> @@ -622,7 +622,7 @@ intel_miptree_get_dimensions_for_image(struct
> gl_texture_image *image,
> int *width, int *height, int *depth);
>
> void
> -intel_miptree_get_tile_masks(uint32_t tiling, uint32_t cpp,
> +intel_miptree_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
> uint32_t *mask_x, uint32_t *mask_y,
> bool map_stencil_as_y_tiled);
>
LGTM, though I wouldn't push this until the user of the new tr mode is reviewed.
Reviewed-by: Ben Widawsky <b...@bwidawsk.net>
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