I misinterpreted the alignmnet restriction in XY_FAST_COPY_BLT earlier.
Instead of checking pitch for 64KB alignmnet we need to check it for
tile widh alignment.
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
Cc: Ben Widawsky <b...@bwidawsk.net>
---
src/mesa/drivers/dri/i965/intel_blit.c | 18 +++++++-----------
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b/src/mesa/drivers/dri/i965/intel_blit.c
index 729ffb0..b85fd3d 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -448,14 +448,6 @@ can_fast_copy_blit(struct brw_context *brw,
(dst_tiling_none && dst_pitch % 16 != 0))
return false;
- /* For Tiled surfaces, the pitch has to be a multiple of the Tile width
- * (X direction width of the Tile). This means the pitch value will
- * always be Cache Line aligned (64byte multiple).
- */
- if ((!dst_tiling_none && dst_pitch % 64 != 0) ||
- (!src_tiling_none && src_pitch % 64 != 0))
- return false;
-
return true;
}
@@ -566,6 +558,13 @@ intelEmitCopyBlit(struct brw_context *brw,
intel_miptree_get_tile_dimensions(dst_tiling, dst_tr_mode, cpp,
&dst_tile_w, &dst_tile_h);
+ /* For Tiled surfaces, the pitch has to be a multiple of the Tile width
+ * (X direction width of the Tile). This is ensured while allocating the
+ * buffer object.
+ */
+ assert(src_tiling == I915_TILING_NONE || (src_pitch % src_tile_w) == 0);
+ assert(dst_tiling == I915_TILING_NONE || (dst_pitch % dst_tile_w) == 0);
+
use_fast_copy_blit = can_fast_copy_blit(brw,
src_buffer,
src_x, src_y,
@@ -604,9 +603,6 @@ intelEmitCopyBlit(struct brw_context *brw,
cpp, use_fast_copy_blit);
} else {
- assert(src_tiling == I915_TILING_NONE || (src_pitch % src_tile_w) == 0);
- assert(dst_tiling == I915_TILING_NONE || (dst_pitch % dst_tile_w) == 0);
-
/* For big formats (such as floating point), do the copy using 16 or
* 32bpp and multiply the coordinates.
*/
--
2.4.3
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