In order to reduce future churn, move the callbacks for starting and
finishing the batch from intel_batchbuffer to the brw_context.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_context.c | 84 +++++++++++++++++++++++++++
src/mesa/drivers/dri/i965/brw_context.h | 3 +
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 78 +------------------------
3 files changed, 89 insertions(+), 76 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 21e6090..45184d9 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -60,6 +60,7 @@
#include "intel_mipmap_tree.h"
#include "intel_pixel.h"
#include "intel_image.h"
+#include "intel_reg.h"
#include "intel_tex.h"
#include "intel_tex_obj.h"
@@ -1492,3 +1493,86 @@ intel_update_image_buffers(struct brw_context *brw,
__DRIdrawable *drawable)
__DRI_IMAGE_BUFFER_BACK);
}
}
+
+/**
+ * Called when starting a new batch buffer.
+ */
+void brw_batch_start_hook(brw_batch *batch)
+{
+ struct brw_context *brw = container_of(batch, brw, batch);
+
+ /* If the kernel supports hardware contexts, then most hardware state is
+ * preserved between batches; we only need to re-emit state that is required
+ * to be in every batch. Otherwise we need to re-emit all the state that
+ * would otherwise be stored in the context (which for all intents and
+ * purposes means everything).
+ */
+ if (!batch->hw_ctx)
+ brw->ctx.NewDriverState |= BRW_NEW_CONTEXT;
+
+ brw->ctx.NewDriverState |= BRW_NEW_BATCH;
+
+ brw->state_batch_count = 0;
+
+ brw->ib.type = -1;
+
+ /* We need to periodically reap the shader time results, because rollover
+ * happens every few seconds. We also want to see results every once in a
+ * while, because many programs won't cleanly destroy our context, so the
+ * end-of-run printout may not happen.
+ */
+ if (INTEL_DEBUG & DEBUG_SHADER_TIME)
+ brw_collect_and_report_shader_time(brw);
+
+ if (INTEL_DEBUG & DEBUG_PERFMON)
+ brw_dump_perf_monitors(brw);
+}
+
+/**
+ * Called from brw_batch_flush before emitting MI_BATCHBUFFER_END and sending
+ * it off.
+ *
+ * This function can emit state (say, to preserve registers that aren't saved
+ * between batches). All of this state MUST fit in the reserved space at the
+ * end of the batchbuffer. If you add more GPU state, increase the reserved
+ * space by updating the BATCH_RESERVED macro.
+ */
+void brw_batch_finish_hook(brw_batch *batch)
+{
+ struct brw_context *brw = container_of(batch, brw, batch);
+
+ if (batch->ring != RENDER_RING)
+ return;
+
+ if (brw->is_haswell) {
+ /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
+ * 3DSTATE_CC_STATE_POINTERS > "Note":
+ *
+ * "SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every
+ * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS
+ * stall."
+ *
+ * From the example in the docs, it seems to expect a regular pipe
control
+ * flush here as well. We may have done it already, but meh.
+ *
+ * See also WaAvoidRCZCounterRollover.
+ */
+ brw_emit_mi_flush(brw);
+
+ BEGIN_BATCH(2);
+ OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
+ OUT_BATCH(brw->cc.state_offset | 1);
+ ADVANCE_BATCH();
+
+ brw_emit_pipe_control_flush(brw,
+ PIPE_CONTROL_RENDER_TARGET_FLUSH |
+ PIPE_CONTROL_CS_STALL);
+ }
+
+ /* Capture the closing pipeline statistics register values necessary to
+ * support query objects (in the non-hardware context world).
+ */
+ brw_emit_query_end(brw);
+
+ brw->cache.bo_used_by_gpu = true;
+}
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index f1fcbd8..1173dfe 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1464,6 +1464,9 @@ struct brw_context
struct intel_screen *intelScreen;
};
+void brw_batch_start_hook(brw_batch *batch);
+void brw_batch_finish_hook(brw_batch *batch);
+
/*======================================================================
* brw_vtbl.c
*/
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index dd5af71..5ad0e63 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -184,81 +184,7 @@ brw_new_batch(struct brw_context *brw)
drm_intel_gem_bo_clear_relocs(brw->batch.bo, 0);
intel_batchbuffer_reset(brw);
- /* If the kernel supports hardware contexts, then most hardware state is
- * preserved between batches; we only need to re-emit state that is required
- * to be in every batch. Otherwise we need to re-emit all the state that
- * would otherwise be stored in the context (which for all intents and
- * purposes means everything).
- */
- if (!brw->batch.hw_ctx)
- brw->ctx.NewDriverState |= BRW_NEW_CONTEXT;
-
- brw->ctx.NewDriverState |= BRW_NEW_BATCH;
-
- brw->state_batch_count = 0;
-
- brw->ib.type = -1;
-
- /* We need to periodically reap the shader time results, because rollover
- * happens every few seconds. We also want to see results every once in a
- * while, because many programs won't cleanly destroy our context, so the
- * end-of-run printout may not happen.
- */
- if (INTEL_DEBUG & DEBUG_SHADER_TIME)
- brw_collect_and_report_shader_time(brw);
-
- if (INTEL_DEBUG & DEBUG_PERFMON)
- brw_dump_perf_monitors(brw);
-}
-
-/**
- * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
- * sending it off.
- *
- * This function can emit state (say, to preserve registers that aren't saved
- * between batches). All of this state MUST fit in the reserved space at the
- * end of the batchbuffer. If you add more GPU state, increase the reserved
- * space by updating the BATCH_RESERVED macro.
- */
-static void
-brw_finish_batch(struct brw_context *brw)
-{
- /* Capture the closing pipeline statistics register values necessary to
- * support query objects (in the non-hardware context world).
- */
- brw_emit_query_end(brw);
-
- if (brw->batch.ring == RENDER_RING) {
- /* We may also need to snapshot and disable OA counters. */
- brw_perf_monitor_finish_batch(brw);
-
- if (brw->is_haswell) {
- /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
- * 3DSTATE_CC_STATE_POINTERS > "Note":
- *
- * "SW must program 3DSTATE_CC_STATE_POINTERS command at the end of
every
- * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS
stall."
- *
- * From the example in the docs, it seems to expect a regular pipe
control
- * flush here as well. We may have done it already, but meh.
- *
- * See also WaAvoidRCZCounterRollover.
- */
- brw_emit_mi_flush(brw);
- BEGIN_BATCH(2);
- OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
- OUT_BATCH(brw->cc.state_offset | 1);
- ADVANCE_BATCH();
- brw_emit_pipe_control_flush(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH |
- PIPE_CONTROL_CS_STALL);
- }
- }
-
- /* Mark that the current program cache BO has been used by the GPU.
- * It will be reallocated if we need to put new programs in for the
- * next batch.
- */
- brw->cache.bo_used_by_gpu = true;
+ brw_batch_start_hook(&brw->batch);
}
static void
@@ -388,7 +314,7 @@ _intel_batchbuffer_flush(struct brw_context *brw,
brw->batch.reserved_space = 0;
- brw_finish_batch(brw);
+ brw_batch_finish_hook(&brw->batch);
/* Mark the end of the buffer. */
intel_batchbuffer_emit_dword(brw, MI_BATCH_BUFFER_END);
--
2.5.0
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