If we have to flush the batchbuffer early that has performance
implications, and if it is a result of user action we should report that
through the perf_debug interface.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_batch.h | 3 ++
src/mesa/drivers/dri/i965/brw_blorp.cpp | 6 +--
src/mesa/drivers/dri/i965/brw_compute.c | 6 +--
src/mesa/drivers/dri/i965/brw_context.c | 52 ++++++++++++++++++++----
src/mesa/drivers/dri/i965/brw_context.h | 25 ++++++++++++
src/mesa/drivers/dri/i965/brw_draw.c | 8 ++--
src/mesa/drivers/dri/i965/brw_queryobj.c | 4 +-
src/mesa/drivers/dri/i965/brw_state_batch.c | 2 +-
src/mesa/drivers/dri/i965/brw_state_cache.c | 2 +-
src/mesa/drivers/dri/i965/gen6_queryobj.c | 2 +-
src/mesa/drivers/dri/i965/gen7_sol_state.c | 22 ++++++----
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 10 +++--
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 14 ++-----
src/mesa/drivers/dri/i965/intel_blit.c | 4 +-
src/mesa/drivers/dri/i965/intel_buffer_objects.c | 6 +--
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
src/mesa/drivers/dri/i965/intel_pixel_bitmap.c | 2 +-
src/mesa/drivers/dri/i965/intel_pixel_copy.c | 2 +-
src/mesa/drivers/dri/i965/intel_pixel_read.c | 6 +--
src/mesa/drivers/dri/i965/intel_screen.c | 2 +-
src/mesa/drivers/dri/i965/intel_syncobj.c | 2 +-
src/mesa/drivers/dri/i965/intel_tex_image.c | 6 +--
src/mesa/drivers/dri/i965/intel_tex_subimage.c | 6 +--
23 files changed, 126 insertions(+), 68 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_batch.h
b/src/mesa/drivers/dri/i965/brw_batch.h
index 705f2f9..782b853 100644
--- a/src/mesa/drivers/dri/i965/brw_batch.h
+++ b/src/mesa/drivers/dri/i965/brw_batch.h
@@ -187,6 +187,9 @@ brw_batch_reloc(brw_batch *batch,
return target_bo->offset64 + target_offset;
}
+struct perf_debug;
+int brw_batch_flush(struct brw_batch *batch, struct perf_debug *info);
+
#ifdef __cplusplus
}
#endif
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 55ccc4f..2e06317 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -260,17 +260,17 @@ retry:
if (!check_aperture_failed_once) {
check_aperture_failed_once = true;
intel_batchbuffer_reset_to_saved(brw);
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, NULL);
goto retry;
} else {
- int ret = intel_batchbuffer_flush(brw);
+ int ret = brw_batch_flush(&brw->batch, NULL);
WARN_ONCE(ret == -ENOSPC,
"i965: blorp emit exceeded available aperture space\n");
}
}
if (unlikely(brw->batch.always_flush))
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, NULL);
/* We've smashed all state compared to what the normal 3D pipeline
* rendering tracks for GL.
diff --git a/src/mesa/drivers/dri/i965/brw_compute.c
b/src/mesa/drivers/dri/i965/brw_compute.c
index c7a184e..c2c39e0 100644
--- a/src/mesa/drivers/dri/i965/brw_compute.c
+++ b/src/mesa/drivers/dri/i965/brw_compute.c
@@ -123,11 +123,11 @@ brw_dispatch_compute(struct gl_context *ctx, const GLuint
*num_groups)
if (dri_bufmgr_check_aperture_space(&brw->batch.bo, 1)) {
if (!fail_next) {
intel_batchbuffer_reset_to_saved(brw);
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, NULL);
fail_next = true;
goto retry;
} else {
- if (intel_batchbuffer_flush(brw) == -ENOSPC) {
+ if (brw_batch_flush(&brw->batch, NULL) == -ENOSPC) {
static bool warned = false;
if (!warned) {
@@ -145,7 +145,7 @@ brw_dispatch_compute(struct gl_context *ctx, const GLuint
*num_groups)
brw_compute_state_finished(brw);
if (brw->batch.always_flush)
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, NULL);
brw_state_cache_check_size(brw);
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 45184d9..e8d43db 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -196,7 +196,8 @@ intel_update_state(struct gl_context * ctx, GLuint
new_state)
#define flushFront(screen) ((screen)->image.loader ?
(screen)->image.loader->flushFrontBuffer :
(screen)->dri2.loader->flushFrontBuffer)
static void
-intel_flush_front(struct gl_context *ctx)
+intel_flush_front(struct gl_context *ctx,
+ struct perf_debug *info)
{
struct brw_context *brw = brw_context(ctx);
__DRIcontext *driContext = brw->driContext;
@@ -214,7 +215,7 @@ intel_flush_front(struct gl_context *ctx)
* performance.
*/
intel_resolve_for_dri2_flush(brw, driDrawable);
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, info);
flushFront(screen)(driDrawable, driDrawable->loaderPrivate);
@@ -225,7 +226,7 @@ intel_flush_front(struct gl_context *ctx)
}
}
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, info);
}
static void
@@ -233,7 +234,7 @@ intel_glFlush(struct gl_context *ctx)
{
struct brw_context *brw = brw_context(ctx);
- intel_flush_front(ctx);
+ intel_flush_front(ctx, PERF_DEBUG(brw, "Flush"));
brw->batch.need_flush_throttle = true;
}
@@ -243,7 +244,7 @@ intel_finish(struct gl_context * ctx)
{
struct brw_context *brw = brw_context(ctx);
- intel_glFlush(ctx);
+ intel_flush_front(ctx, PERF_DEBUG(brw, "Finish"));
if (brw->batch.last_bo)
drm_intel_bo_wait_rendering(brw->batch.last_bo);
@@ -899,7 +900,7 @@ intelDestroyContext(__DRIcontext * driContextPriv)
/* Dump a final BMP in case the application doesn't call SwapBuffers */
if (INTEL_DEBUG & DEBUG_AUB) {
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, NULL);
aub_dump_bmp(&brw->ctx);
}
@@ -1272,7 +1273,7 @@ intel_query_dri2_buffers(struct brw_context *brw,
* query, we need to make sure all the pending drawing has landed in the
* real front buffer.
*/
- intel_flush_front(&brw->ctx);
+ intel_flush_front(&brw->ctx, NULL);
attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
attachments[i++] = intel_bits_per_pixel(front_rb);
@@ -1283,7 +1284,7 @@ intel_query_dri2_buffers(struct brw_context *brw,
* So before doing the query, make sure all the pending drawing has
* landed in the real front buffer.
*/
- intel_flush_front(&brw->ctx);
+ intel_flush_front(&brw->ctx, NULL);
}
if (back_rb) {
@@ -1576,3 +1577,38 @@ void brw_batch_finish_hook(brw_batch *batch)
brw->cache.bo_used_by_gpu = true;
}
+
+void brw_batch_report_flush_hook(struct brw_batch *batch,
+ struct perf_debug *info)
+{
+ struct brw_context *brw = container_of(batch, brw, batch);
+
+ if (unlikely(INTEL_DEBUG & DEBUG_PERF))
+ dbg_printf("%s (%s:%s:%d) triggered batch flush\n",
+ info->string, info->file, info->function, info->line);
+
+ _mesa_gl_debug(&brw->ctx, &info->flush_msg_id,
+ MESA_DEBUG_SOURCE_API,
+ MESA_DEBUG_TYPE_PERFORMANCE,
+ MESA_DEBUG_SEVERITY_LOW,
+ "%s caused early batch flush\n",
+ info->string);
+}
+
+void brw_batch_report_stall_hook(struct brw_batch *batch,
+ struct perf_debug *info)
+{
+ struct brw_context *brw = container_of(batch, brw, batch);
+
+ if (unlikely(INTEL_DEBUG & DEBUG_PERF))
+ dbg_printf("%s (%s:%s:%d) stalled for %.3fms\n",
+ info->string, info->file, info->function, info->line,
+ 1e3*info->elapsed);
+
+ _mesa_gl_debug(&brw->ctx, &info->stall_msg_id,
+ MESA_DEBUG_SOURCE_API,
+ MESA_DEBUG_TYPE_PERFORMANCE,
+ MESA_DEBUG_SEVERITY_MEDIUM,
+ "%s stalled for %.3fms\n",
+ info->string, 1e3*info->elapsed);
+}
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 1173dfe..d89016e 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1467,6 +1467,31 @@ struct brw_context
void brw_batch_start_hook(brw_batch *batch);
void brw_batch_finish_hook(brw_batch *batch);
+struct perf_debug {
+ const char *string;
+ const char *file;
+ const char *function;
+ int line;
+ GLuint flush_msg_id;
+ GLuint stall_msg_id;
+ double elapsed;
+};
+#define PERF_DEBUG(brw, str) ({\
+ struct perf_debug *__info = NULL; \
+ if (unlikely((brw)->perf_debug)) { \
+ static struct perf_debug __static_perf_debug__ = { \
+ (str), __FILE__, __FUNCTION__, __LINE__, \
+ }; \
+ __info = &__static_perf_debug__; \
+ } \
+ __info; \
+})
+
+void brw_batch_report_flush_hook(brw_batch *batch,
+ struct perf_debug *info);
+void brw_batch_report_stall_hook(brw_batch *batch,
+ struct perf_debug *info);
+
/*======================================================================
* brw_vtbl.c
*/
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 53364a1..b5c343a 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -504,7 +504,7 @@ retry:
/* Note that before the loop, brw->ctx.NewDriverState was set to != 0,
and
* that the state updated in the loop outside of this block is that in
- * *_set_prim or intel_batchbuffer_flush(), which only impacts
+ * *_set_prim or brw_batch_flush(), which only impacts
* brw->ctx.NewDriverState.
*/
if (brw->ctx.NewDriverState) {
@@ -519,11 +519,11 @@ retry:
if (dri_bufmgr_check_aperture_space(&brw->batch.bo, 1)) {
if (!fail_next) {
intel_batchbuffer_reset_to_saved(brw);
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, NULL);
fail_next = true;
goto retry;
} else {
- int ret = intel_batchbuffer_flush(brw);
+ int ret = brw_batch_flush(&brw->batch, NULL);
WARN_ONCE(ret == -ENOSPC,
"i965: Single primitive emit exceeded "
"available aperture space\n");
@@ -538,7 +538,7 @@ retry:
}
if (brw->batch.always_flush)
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, NULL);
brw_state_cache_check_size(brw);
brw_postdraw_set_buffers_need_resolve(brw);
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c
b/src/mesa/drivers/dri/i965/brw_queryobj.c
index 51ba2d6..e0226a1 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -104,7 +104,7 @@ brw_queryobj_get_results(struct gl_context *ctx,
* when mapped.
*/
if (drm_intel_bo_references(brw->batch.bo, query->bo))
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, PERF_DEBUG(brw, "GetQuery"));
if (unlikely(brw->perf_debug)) {
if (drm_intel_bo_busy(query->bo)) {
@@ -364,7 +364,7 @@ static void brw_check_query(struct gl_context *ctx, struct
gl_query_object *q)
* the async query will return true in finite time.
*/
if (query->bo && drm_intel_bo_references(brw->batch.bo, query->bo))
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, PERF_DEBUG(brw, "CheckQuery"));
if (query->bo == NULL || !drm_intel_bo_busy(query->bo)) {
brw_queryobj_get_results(ctx, query);
diff --git a/src/mesa/drivers/dri/i965/brw_state_batch.c
b/src/mesa/drivers/dri/i965/brw_state_batch.c
index 22dfbe5..fa0dc6f 100644
--- a/src/mesa/drivers/dri/i965/brw_state_batch.c
+++ b/src/mesa/drivers/dri/i965/brw_state_batch.c
@@ -134,7 +134,7 @@ __brw_state_batch(struct brw_context *brw,
*/
if (batch->state_batch_offset < size ||
offset < 4 * USED_BATCH(*batch) + batch->reserved_space) {
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, NULL);
offset = ROUND_DOWN_TO(batch->state_batch_offset - size, alignment);
}
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c
b/src/mesa/drivers/dri/i965/brw_state_cache.c
index e2dbcc6..3ba12c4 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -401,7 +401,7 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache
*cache)
*/
brw->NewGLState |= ~0;
brw->ctx.NewDriverState |= ~0ull;
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, NULL);
}
void
diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c
b/src/mesa/drivers/dri/i965/gen6_queryobj.c
index dfacfbd..e291f90 100644
--- a/src/mesa/drivers/dri/i965/gen6_queryobj.c
+++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c
@@ -410,7 +410,7 @@ flush_batch_if_needed(struct brw_context *brw, struct
brw_query_object *query)
!drm_intel_bo_references(brw->batch.bo, query->bo);
if (!query->flushed)
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, PERF_DEBUG(brw, "GetQuery"));
}
/**
diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c
b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index 8eca604..b07ab91 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -310,13 +310,14 @@ const struct brw_tracked_state gen7_sol_state = {
*/
static void
gen7_tally_prims_generated(struct brw_context *brw,
- struct brw_transform_feedback_object *obj)
+ struct brw_transform_feedback_object *obj,
+ struct perf_debug *perf)
{
/* If the current batch is still contributing to the number of primitives
* generated, flush it now so the results will be present when mapped.
*/
if (drm_intel_bo_references(brw->batch.bo, obj->prim_count_bo))
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, perf);
if (unlikely(brw->perf_debug && drm_intel_bo_busy(obj->prim_count_bo)))
perf_debug("Stalling for # of transform feedback primitives written.\n");
@@ -354,7 +355,7 @@ gen7_tally_prims_generated(struct brw_context *brw,
*/
static void
gen7_save_primitives_written_counters(struct brw_context *brw,
- struct brw_transform_feedback_object *obj)
+ struct brw_transform_feedback_object
*obj)
{
const int streams = BRW_MAX_XFB_STREAMS;
@@ -362,7 +363,7 @@ gen7_save_primitives_written_counters(struct brw_context
*brw,
if (obj->prim_count_bo != NULL &&
obj->prim_count_buffer_index + 2 * streams >= 4096 / sizeof(uint64_t)) {
/* Gather up the results so far and release the BO. */
- gen7_tally_prims_generated(brw, obj);
+ gen7_tally_prims_generated(brw, obj, NULL);
}
/* Flush any drawing so that the counters have the right values. */
@@ -384,7 +385,8 @@ gen7_save_primitives_written_counters(struct brw_context
*brw,
*/
static void
brw_compute_xfb_vertices_written(struct brw_context *brw,
- struct brw_transform_feedback_object *obj)
+ struct brw_transform_feedback_object *obj,
+ struct perf_debug *perf)
{
if (obj->vertices_written_valid || !obj->base.EndedAnytime)
return;
@@ -406,7 +408,7 @@ brw_compute_xfb_vertices_written(struct brw_context *brw,
}
/* Get the number of primitives generated. */
- gen7_tally_prims_generated(brw, obj);
+ gen7_tally_prims_generated(brw, obj, perf);
for (int i = 0; i < BRW_MAX_XFB_STREAMS; i++) {
obj->vertices_written[i] = vertices_per_prim * obj->prims_generated[i];
@@ -432,7 +434,8 @@ brw_get_transform_feedback_vertex_count(struct gl_context
*ctx,
assert(obj->EndedAnytime);
assert(stream < BRW_MAX_XFB_STREAMS);
- brw_compute_xfb_vertices_written(brw, brw_obj);
+ brw_compute_xfb_vertices_written(brw, brw_obj,
+ PERF_DEBUG(brw, "GetTransformFeedback"));
return brw_obj->vertices_written[stream];
}
@@ -448,7 +451,7 @@ gen7_begin_transform_feedback(struct gl_context *ctx,
GLenum mode,
if (brw->gen >= 8) {
brw_obj->zero_offsets = true;
} else if (!brw->has_pipelined_so) {
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, PERF_DEBUG(brw, "BeginTransformFeedback"));
brw->batch.needs_sol_reset = true;
}
@@ -456,7 +459,8 @@ gen7_begin_transform_feedback(struct gl_context *ctx,
GLenum mode,
* vertices written during the last Begin/EndTransformFeedback section,
* so we can't delay it any further.
*/
- brw_compute_xfb_vertices_written(brw, brw_obj);
+ brw_compute_xfb_vertices_written(brw, brw_obj,
+ PERF_DEBUG(brw, "BeginTransformFeedback"));
/* No primitives have been generated yet. */
for (int i = 0; i < BRW_MAX_XFB_STREAMS; i++) {
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 5ad0e63..44de240 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -290,9 +290,9 @@ do_flush_locked(struct brw_context *brw)
}
int
-_intel_batchbuffer_flush(struct brw_context *brw,
- const char *file, int line)
+brw_batch_flush(struct brw_batch *batch, struct perf_debug *info)
{
+ struct brw_context *brw = container_of(batch, brw, batch);
int ret;
if (USED_BATCH(brw->batch) == 0)
@@ -306,12 +306,16 @@ _intel_batchbuffer_flush(struct brw_context *brw,
int bytes_for_state = brw->batch.bo->size -
brw->batch.state_batch_offset;
int total_bytes = bytes_for_commands + bytes_for_state;
fprintf(stderr, "%s:%d: Batchbuffer flush with %4db (pkt) + "
- "%4db (state) = %4db (%0.1f%%)\n", file, line,
+ "%4db (state) = %4db (%0.1f%%)\n",
+ info ? info->file : "???", info ? info->line : -1,
bytes_for_commands, bytes_for_state,
total_bytes,
100.0f * total_bytes / BATCH_SZ);
}
+ if (unlikely(info))
+ brw_batch_report_flush_hook(batch, info);
+
brw->batch.reserved_space = 0;
brw_batch_finish_hook(&brw->batch);
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index 9e32aea..f8236bb 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -42,14 +42,6 @@ void intel_batchbuffer_free(struct brw_context *brw);
void intel_batchbuffer_save_state(struct brw_context *brw);
void intel_batchbuffer_reset_to_saved(struct brw_context *brw);
-int _intel_batchbuffer_flush(struct brw_context *brw,
- const char *file, int line);
-
-#define intel_batchbuffer_flush(intel) \
- _intel_batchbuffer_flush(intel, __FILE__, __LINE__)
-
-
-
/* Unlike bmBufferData, this currently requires the buffer be mapped.
* Consider it a convenience function wrapping multple
* intel_buffer_dword() calls.
@@ -120,17 +112,17 @@ intel_batchbuffer_require_space(struct brw_context *brw,
GLuint sz,
/* If we're switching rings, implicitly flush the batch. */
if (unlikely(ring != brw->batch.ring) && brw->batch.ring != UNKNOWN_RING &&
brw->gen >= 6) {
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, NULL);
}
#ifdef DEBUG
assert(sz < BATCH_SZ - BATCH_RESERVED);
#endif
if (intel_batchbuffer_space(brw) < sz)
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, NULL);
enum brw_gpu_ring prev_ring = brw->batch.ring;
- /* The intel_batchbuffer_flush() calls above might have changed
+ /* The brw_batch_flush() calls above might have changed
* brw->batch.ring to UNKNOWN_RING, so we need to set it here at the end.
*/
brw->batch.ring = ring;
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b/src/mesa/drivers/dri/i965/intel_blit.c
index 91ffcef..750550d 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -539,7 +539,7 @@ intelEmitCopyBlit(struct brw_context *brw,
aper_array[2] = src_buffer;
if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, NULL);
pass++;
} else
break;
@@ -877,7 +877,7 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw,
if (drm_intel_bufmgr_check_aperture_space(aper_array,
ARRAY_SIZE(aper_array)) != 0) {
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, NULL);
}
unsigned length = brw->gen >= 8 ? 7 : 6;
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index a45f8e0..fcbec9a 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -303,7 +303,7 @@ brw_buffer_subdata(struct gl_context *ctx,
(long)offset, (long)offset + size, (long)(size/1024),
intel_obj->gpu_active_start,
intel_obj->gpu_active_end);
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, PERF_DEBUG(brw, "BufferSubData"));
}
}
@@ -330,7 +330,7 @@ brw_get_buffer_subdata(struct gl_context *ctx,
assert(intel_obj);
if (drm_intel_bo_references(brw->batch.bo, intel_obj->buffer)) {
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, PERF_DEBUG(brw, "BufferSubData"));
}
drm_intel_bo_get_subdata(intel_obj->buffer, offset, size, data);
@@ -395,7 +395,7 @@ brw_map_buffer_range(struct gl_context *ctx,
} else {
perf_debug("Stalling on the GPU for mapping a busy buffer "
"object\n");
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, PERF_DEBUG(brw, "miptree"));
}
} else if (drm_intel_bo_busy(intel_obj->buffer) &&
(access & GL_MAP_INVALIDATE_BUFFER_BIT)) {
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 17c5f33..fce6e37 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2067,7 +2067,7 @@ intel_miptree_map_raw(struct brw_context *brw, struct
intel_mipmap_tree *mt)
brw_bo *bo = mt->bo;
if (drm_intel_bo_references(brw->batch.bo, bo))
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, PERF_DEBUG(brw, "miptree"));
if (mt->tiling != I915_TILING_NONE)
brw_bo_map_gtt(brw, bo, "miptree");
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
index dd5ae1d..61ece9e 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
@@ -313,7 +313,7 @@ do_blit_bitmap( struct gl_context *ctx,
out:
if (unlikely(INTEL_DEBUG & DEBUG_SYNC))
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, NULL);
if (_mesa_is_bufferobj(unpack->BufferObj)) {
/* done with PBO so unmap it now */
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_copy.c
b/src/mesa/drivers/dri/i965/intel_pixel_copy.c
index 668c29b..f1013ff 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_copy.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_copy.c
@@ -148,7 +148,7 @@ do_blit_copypixels(struct gl_context * ctx,
return false;
}
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, PERF_DEBUG(brw, "CopyPixels"));
/* Clip to destination buffer. */
orig_dstx = dstx;
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c
b/src/mesa/drivers/dri/i965/intel_pixel_read.c
index f1f585f..ce71a75 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c
@@ -156,10 +156,8 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx,
bo = irb->mt->bo;
- if (drm_intel_bo_references(brw->batch.bo, bo)) {
- perf_debug("Flushing before mapping a referenced bo.\n");
- intel_batchbuffer_flush(brw);
- }
+ if (drm_intel_bo_references(brw->batch.bo, bo))
+ brw_batch_flush(&brw->batch, PERF_DEBUG(brw, "ReadPixels"));
error = brw_bo_map(brw, bo, false /* write enable */, "miptree");
if (error) {
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index 5b3ad24..efd5abd 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -181,7 +181,7 @@ intel_dri2_flush_with_flags(__DRIcontext *cPriv,
if (reason == __DRI2_THROTTLE_FLUSHFRONT)
brw->batch.need_flush_throttle = true;
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, NULL);
if (INTEL_DEBUG & DEBUG_AUB) {
aub_dump_bmp(ctx);
diff --git a/src/mesa/drivers/dri/i965/intel_syncobj.c
b/src/mesa/drivers/dri/i965/intel_syncobj.c
index b05a741..2faf953 100644
--- a/src/mesa/drivers/dri/i965/intel_syncobj.c
+++ b/src/mesa/drivers/dri/i965/intel_syncobj.c
@@ -69,7 +69,7 @@ brw_fence_insert(struct brw_context *brw, struct brw_fence
*fence)
brw_emit_mi_flush(brw);
fence->batch_bo = brw_bo_get(brw->batch.bo);
- intel_batchbuffer_flush(brw);
+ brw_batch_flush(&brw->batch, PERF_DEBUG(brw, "SyncFence"));
}
static bool
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 8b2ec0f..0ce63ef 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -427,10 +427,8 @@ intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx,
bo = image->mt->bo;
- if (drm_intel_bo_references(brw->batch.bo, bo)) {
- perf_debug("Flushing before mapping a referenced bo.\n");
- intel_batchbuffer_flush(brw);
- }
+ if (drm_intel_bo_references(brw->batch.bo, bo))
+ brw_batch_flush(&brw->batch, PERF_DEBUG(brw, "miptree"));
error = brw_bo_map(brw, bo, false /* write enable */, "miptree");
if (error) {
diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
index c771af9..79341d7 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
@@ -142,10 +142,8 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
bo = image->mt->bo;
- if (drm_intel_bo_references(brw->batch.bo, bo)) {
- perf_debug("Flushing before mapping a referenced bo.\n");
- intel_batchbuffer_flush(brw);
- }
+ if (drm_intel_bo_references(brw->batch.bo, bo))
+ brw_batch_flush(&brw->batch, PERF_DEBUG(brw, "miptree"));
error = brw_bo_map(brw, bo, true /* write enable */, "miptree");
if (error || bo->virtual == NULL) {
--
2.5.0
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