In order to track aperture usage correctly and flush the batch at safe
transition points, we need to wrap all batch buffer access in begin/end
introduced in the previous patch.
Note, this patch doesn't transform everything - we leave the small
flushes to a later refactor and treat brw_performance_monitor.c
separately as it deserves more careful attention.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_conditional_render.c | 5 +++++
src/mesa/drivers/dri/i965/brw_queryobj.c | 15 +++++++++++++++
src/mesa/drivers/dri/i965/brw_state_upload.c | 12 ++++++++++--
src/mesa/drivers/dri/i965/gen6_queryobj.c | 10 ++++++++++
src/mesa/drivers/dri/i965/gen7_sol_state.c | 20 ++++++++++++++++++++
src/mesa/drivers/dri/i965/gen8_depth_state.c | 10 ++++++++++
6 files changed, 70 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_conditional_render.c
b/src/mesa/drivers/dri/i965/brw_conditional_render.c
index 962c1f1..9362468 100644
--- a/src/mesa/drivers/dri/i965/brw_conditional_render.c
+++ b/src/mesa/drivers/dri/i965/brw_conditional_render.c
@@ -57,6 +57,9 @@ set_predicate_for_result(struct brw_context *brw,
assert(query->bo != NULL);
+ if (brw_batch_begin(&brw->batch, 60, RENDER_RING) < 0)
+ return;
+
brw_load_register_mem64(brw,
MI_PREDICATE_SRC0,
query->bo,
@@ -82,6 +85,8 @@ set_predicate_for_result(struct brw_context *brw,
MI_PREDICATE_COMPAREOP_SRCS_EQUAL);
ADVANCE_BATCH();
+ brw_batch_end(&brw->batch);
+
brw->predicate.state = BRW_PREDICATE_STATE_USE_BIT;
}
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c
b/src/mesa/drivers/dri/i965/brw_queryobj.c
index e0226a1..28d01c1 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -214,6 +214,9 @@ brw_begin_query(struct gl_context *ctx, struct
gl_query_object *q)
assert(brw->gen < 6);
+ if (brw_batch_begin(&brw->batch, 60, RENDER_RING) < 0)
+ return;
+
switch (query->Base.Target) {
case GL_TIME_ELAPSED_EXT:
/* For timestamp queries, we record the starting time right away so that
@@ -268,6 +271,8 @@ brw_begin_query(struct gl_context *ctx, struct
gl_query_object *q)
default:
unreachable("Unrecognized query target in brw_begin_query()");
}
+
+ brw_batch_end(&brw->batch);
}
/**
@@ -286,6 +291,9 @@ brw_end_query(struct gl_context *ctx, struct
gl_query_object *q)
assert(brw->gen < 6);
+ if (brw_batch_begin(&brw->batch, 60, RENDER_RING) < 0)
+ return;
+
switch (query->Base.Target) {
case GL_TIME_ELAPSED_EXT:
/* Write the final timestamp. */
@@ -325,6 +333,8 @@ brw_end_query(struct gl_context *ctx, struct
gl_query_object *q)
default:
unreachable("Unrecognized query target in brw_end_query()");
}
+
+ brw_batch_end(&brw->batch);
}
/**
@@ -484,7 +494,12 @@ brw_query_counter(struct gl_context *ctx, struct
gl_query_object *q)
brw_bo_put(query->bo);
query->bo = brw_bo_create(&brw->batch, "timestamp query",
4096, 4096, BO_ALLOC_FOR_RENDER);
+
+ if (brw_batch_begin(&brw->batch, 60, RENDER_RING) < 0)
+ return;
+
brw_write_timestamp(brw, query->bo, 0);
+ brw_batch_end(&brw->batch);
query->flushed = false;
}
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 1d94172..ea15f9d 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -343,15 +343,21 @@ static const struct brw_tracked_state
*gen8_compute_atoms[] =
&brw_cs_state,
};
-static void
+static int
brw_upload_initial_gpu_state(struct brw_context *brw)
{
+ int ret;
+
/* On platforms with hardware contexts, we can set our initial GPU state
* right away rather than doing it via state atoms. This saves a small
* amount of overhead on every draw call.
*/
if (!brw->batch.hw_ctx)
- return;
+ return 0;
+
+ ret = brw_batch_begin(&brw->batch, 200, RENDER_RING);
+ if (ret < 0)
+ return ret;
if (brw->gen == 6)
brw_emit_post_sync_nonzero_flush(brw);
@@ -369,6 +375,8 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
if (brw->gen >= 8) {
gen8_emit_3dstate_sample_pattern(brw);
}
+
+ return brw_batch_end(&brw->batch);
}
static inline const struct brw_tracked_state *
diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c
b/src/mesa/drivers/dri/i965/gen6_queryobj.c
index e291f90..935dcfe 100644
--- a/src/mesa/drivers/dri/i965/gen6_queryobj.c
+++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c
@@ -282,6 +282,9 @@ gen6_begin_query(struct gl_context *ctx, struct
gl_query_object *q)
query->bo = brw_bo_create(&brw->batch, "query results",
4096, 4096, BO_ALLOC_FOR_RENDER);
+ if (brw_batch_begin(&brw->batch, 120, RENDER_RING) < 0)
+ return;
+
switch (query->Base.Target) {
case GL_TIME_ELAPSED:
/* For timestamp queries, we record the starting time right away so that
@@ -337,6 +340,8 @@ gen6_begin_query(struct gl_context *ctx, struct
gl_query_object *q)
default:
unreachable("Unrecognized query target in brw_begin_query()");
}
+
+ brw_batch_end(&brw->batch);
}
/**
@@ -353,6 +358,9 @@ gen6_end_query(struct gl_context *ctx, struct
gl_query_object *q)
struct brw_context *brw = brw_context(ctx);
struct brw_query_object *query = (struct brw_query_object *)q;
+ if (brw_batch_begin(&brw->batch, 120, RENDER_RING) < 0)
+ return;
+
switch (query->Base.Target) {
case GL_TIME_ELAPSED:
brw_write_timestamp(brw, query->bo, 1);
@@ -391,6 +399,8 @@ gen6_end_query(struct gl_context *ctx, struct
gl_query_object *q)
unreachable("Unrecognized query target in brw_end_query()");
}
+ brw_batch_end(&brw->batch);
+
/* The current batch contains the commands to handle EndQuery(),
* but they won't actually execute until it is flushed.
*/
diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c
b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index b07ab91..b177521 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -462,6 +462,9 @@ gen7_begin_transform_feedback(struct gl_context *ctx,
GLenum mode,
brw_compute_xfb_vertices_written(brw, brw_obj,
PERF_DEBUG(brw, "BeginTransformFeedback"));
+ if (brw_batch_begin(&brw->batch, 300, RENDER_RING) < 0)
+ return;
+
/* No primitives have been generated yet. */
for (int i = 0; i < BRW_MAX_XFB_STREAMS; i++) {
brw_obj->prims_generated[i] = 0;
@@ -477,6 +480,8 @@ gen7_begin_transform_feedback(struct gl_context *ctx,
GLenum mode,
/* Store the starting value of the SO_NUM_PRIMS_WRITTEN counters. */
gen7_save_primitives_written_counters(brw, brw_obj);
+ brw_batch_end(&brw->batch);
+
brw_obj->primitive_mode = mode;
}
@@ -494,9 +499,14 @@ gen7_end_transform_feedback(struct gl_context *ctx,
struct brw_transform_feedback_object *brw_obj =
(struct brw_transform_feedback_object *) obj;
+ if (brw_batch_begin(&brw->batch, 300, RENDER_RING) < 0)
+ return;
+
/* Store the ending value of the SO_NUM_PRIMS_WRITTEN counters. */
gen7_save_primitives_written_counters(brw, brw_obj);
+ brw_batch_end(&brw->batch);
+
/* EndTransformFeedback() means that we need to update the number of
* vertices written. Since it's only necessary if DrawTransformFeedback()
* is called and it means mapping a buffer object, we delay computing it
@@ -513,6 +523,9 @@ gen7_pause_transform_feedback(struct gl_context *ctx,
struct brw_transform_feedback_object *brw_obj =
(struct brw_transform_feedback_object *) obj;
+ if (brw_batch_begin(&brw->batch, 300, RENDER_RING) < 0)
+ return;
+
/* Flush any drawing so that the counters have the right values. */
brw_emit_mi_flush(brw);
@@ -535,6 +548,8 @@ gen7_pause_transform_feedback(struct gl_context *ctx,
* from our counts.
*/
gen7_save_primitives_written_counters(brw, brw_obj);
+
+ brw_batch_end(&brw->batch);
}
void
@@ -545,6 +560,9 @@ gen7_resume_transform_feedback(struct gl_context *ctx,
struct brw_transform_feedback_object *brw_obj =
(struct brw_transform_feedback_object *) obj;
+ if (brw_batch_begin(&brw->batch, 300, RENDER_RING) < 0)
+ return;
+
/* Reload the SOL buffer offset registers. */
if (brw->gen < 8) {
for (int i = 0; i < 4; i++) {
@@ -559,4 +577,6 @@ gen7_resume_transform_feedback(struct gl_context *ctx,
/* Store the new starting value of the SO_NUM_PRIMS_WRITTEN counters. */
gen7_save_primitives_written_counters(brw, brw_obj);
+
+ brw_batch_end(&brw->batch);
}
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 82c033d..f8ffbeb 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -399,6 +399,9 @@ gen8_hiz_exec(struct brw_context *brw, struct
intel_mipmap_tree *mt,
if (op == GEN6_HIZ_OP_NONE)
return;
+ if (brw_batch_begin(&brw->batch, 1000, RENDER_RING) < 0)
+ return;
+
/* Disable the PMA stall fix since we're about to do a HiZ operation. */
if (brw->gen == 8)
write_pma_stall_bits(brw, 0);
@@ -509,6 +512,13 @@ gen8_hiz_exec(struct brw_context *brw, struct
intel_mipmap_tree *mt,
/* Mark this buffer as needing a TC flush, as we've rendered to it. */
brw_bo_mark_dirty(&brw->batch, mt->bo);
+ if (brw_batch_end(&brw->batch)) {
+ struct gl_context *ctx = &brw->ctx;
+ WARN_ONCE(1, "i965: blorp emit exceeded available aperture space\n");
+ }
+
+ brw_batch_maybe_flush(&brw->batch);
+
/* We've clobbered all of the depth packets, and the drawing rectangle,
* so we need to ensure those packets are re-emitted before the next
* primitive.
--
2.5.0
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