Well, I could try, but I don't believe I have enough cred yet, to make any difference.
Reviewed-by: "Lofstedt, Marta" <marta.lofst...@intel.com> > -----Original Message----- > From: Francisco Jerez [mailto:curroje...@riseup.net] > Sent: Friday, July 31, 2015 2:07 PM > To: Lofstedt, Marta; mesa-dev@lists.freedesktop.org > Subject: RE: [PATCH] i965/fs: Fix regression with SIMD8 VS since > b5f1a48e234d47b24df38cb562cffb8941d43795. > > "Lofstedt, Marta" <marta.lofst...@intel.com> writes: > > > In hope of speeding up the review and merge of this bug fix, I > > confirm that below patch fix the regression I have had from: > > "b5f1a48e234d47b24df38cb562cffb8941d43795" on Gen8. > > > Wouldn't you feel like reviewing it yourself? :) > > > /Marta > > > >> -----Original Message----- > >> From: Francisco Jerez [mailto:curroje...@riseup.net] > >> Sent: Thursday, July 30, 2015 2:23 PM > >> To: mesa-dev@lists.freedesktop.org > >> Cc: Lofstedt, Marta > >> Subject: [PATCH] i965/fs: Fix regression with SIMD8 VS since > >> b5f1a48e234d47b24df38cb562cffb8941d43795. > >> > >> With num_direct_uniforms == 0 there's no space allocated in the > >> param_size array for the one block of direct uniforms -- On the FS > >> stage this would be a harmless no-op because it would simply re-set > >> one of the param_size entries allocated for the sampler units to > >> zero, but on the VS stage it has been reported to cause memory > >> corruption followed by a crash -- Surprising how a full piglit run on Gen8 > didn't catch it. > >> > >> Reported-by: Marta Lofstedt <marta.lofst...@intel.com> > >> --- > >> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 3 ++- > >> 1 file changed, 2 insertions(+), 1 deletion(-) > >> > >> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp > >> b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp > >> index 722e4e7..9cb7b0d 100644 > >> --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp > >> +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp > >> @@ -182,7 +182,8 @@ fs_visitor::nir_setup_uniforms(nir_shader > *shader) > >> /* We split the uniform register file in half. The first half is > >> * entirely direct uniforms. The second half is indirect. > >> */ > >> - param_size[0] = num_direct_uniforms; > >> + if (num_direct_uniforms > 0) > >> + param_size[0] = num_direct_uniforms; > >> if (shader->num_uniforms > num_direct_uniforms) > >> param_size[num_direct_uniforms] = shader->num_uniforms - > >> num_direct_uniforms; > >> > >> -- > >> 2.4.6 > > > > ---------------------------------------------------------------------- > > Intel Sweden AB > > Registered Office: Knarrarnasgatan 15, 164 40 Kista, Stockholm, Sweden > > Registration Number: 556189-6027 > > > > This e-mail and any attachments may contain confidential material for > > the sole use of the intended recipient(s). Any review or distribution > > by others is strictly prohibited. If you are not the intended > > recipient, please contact the sender and delete all copies. ---------------------------------------------------------------------- Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40 Kista, Stockholm, Sweden Registration Number: 556189-6027 This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
