"Pohjolainen, Topi" <topi.pohjolai...@intel.com> writes: > On Fri, Feb 27, 2015 at 05:34:54PM +0200, Francisco Jerez wrote: >> --- >> src/mesa/drivers/dri/i965/brw_defines.h | 1 + >> src/mesa/drivers/dri/i965/brw_eu.h | 7 +++ >> src/mesa/drivers/dri/i965/brw_eu_emit.c | 51 >> ++++++++++++++++++++++ >> src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++ >> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 6 +++ >> .../drivers/dri/i965/brw_schedule_instructions.cpp | 1 + >> src/mesa/drivers/dri/i965/brw_shader.cpp | 3 ++ >> src/mesa/drivers/dri/i965/brw_vec4.cpp | 2 + >> src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 6 +++ >> 9 files changed, 81 insertions(+) > > Just a few formatting nits: > > Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> > Okay, I've taken your suggestions into account. Thanks!
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
>> b/src/mesa/drivers/dri/i965/brw_defines.h
>> index 7660feb..e56f49c 100644
>> --- a/src/mesa/drivers/dri/i965/brw_defines.h
>> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
>> @@ -904,6 +904,7 @@ enum opcode {
>>
>> SHADER_OPCODE_UNTYPED_ATOMIC,
>> SHADER_OPCODE_UNTYPED_SURFACE_READ,
>> + SHADER_OPCODE_UNTYPED_SURFACE_WRITE,
>>
>> SHADER_OPCODE_GEN4_SCRATCH_READ,
>> SHADER_OPCODE_GEN4_SCRATCH_WRITE,
>> diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
>> b/src/mesa/drivers/dri/i965/brw_eu.h
>> index 9cc9123..cad956b 100644
>> --- a/src/mesa/drivers/dri/i965/brw_eu.h
>> +++ b/src/mesa/drivers/dri/i965/brw_eu.h
>> @@ -414,6 +414,13 @@ brw_untyped_surface_read(struct brw_compile *p,
>> unsigned num_channels);
>>
>> void
>> +brw_untyped_surface_write(struct brw_compile *p,
>> + struct brw_reg payload,
>> + struct brw_reg surface,
>> + unsigned msg_length,
>> + unsigned num_channels);
>> +
>> +void
>> brw_pixel_interpolator_query(struct brw_compile *p,
>> struct brw_reg dest,
>> struct brw_reg mrf,
>> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> b/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> index 34695bf..f5b8fa9 100644
>> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> @@ -2893,6 +2893,57 @@ brw_untyped_surface_read(struct brw_compile *p,
>> p, insn, num_channels);
>> }
>>
>> +static void
>> +brw_set_dp_untyped_surface_write_message(struct brw_compile *p,
>> + struct brw_inst *insn,
>> + unsigned num_channels)
>> +{
>> + const struct brw_context *brw = p->brw;
>> + /* Set mask of 32-bit channels to drop. */
>> + unsigned msg_control = (0xf & (0xf << num_channels));
>
> Could drop the extra () here.
>
>> +
>> + if (brw_inst_access_mode(brw, p->current) == BRW_ALIGN_1) {
>> + if (p->compressed)
>> + msg_control |= 1 << 4; /* SIMD16 mode */
>> + else
>> + msg_control |= 2 << 4; /* SIMD8 mode */
>> + } else {
>> + if (brw->gen >= 8 || brw->is_haswell)
>> + msg_control |= 0 << 4; /* SIMD4x2 mode */
>> + else
>> + msg_control |= 2 << 4; /* SIMD8 mode */
>> + }
>> +
>> + brw_inst_set_dp_msg_type(brw, insn,
>> + (brw->gen >= 8 || brw->is_haswell ?
>> + HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE :
>> + GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE));
>
> Same here.
>
>> + brw_inst_set_dp_msg_control(brw, insn, msg_control);
>> +}
>> +
>> +void
>> +brw_untyped_surface_write(struct brw_compile *p,
>> + struct brw_reg payload,
>> + struct brw_reg surface,
>> + unsigned msg_length,
>> + unsigned num_channels)
>> +{
>> + const struct brw_context *brw = p->brw;
>> + const unsigned sfid = (brw->gen >= 8 || p->brw->is_haswell ?
>> + HSW_SFID_DATAPORT_DATA_CACHE_1 :
>> + GEN7_SFID_DATAPORT_DATA_CACHE);
>> + const bool align1 = (brw_inst_access_mode(brw, p->current) ==
>> BRW_ALIGN_1);
>
> And here.
>
>> + /* Mask out unused components -- See comment in brw_untyped_atomic(). */
>> + const unsigned mask = (brw->gen == 7 && !brw->is_haswell && !align1 ?
>> + WRITEMASK_X : WRITEMASK_XYZW);
>
> And here.
>
>> + struct brw_inst *insn = brw_send_indirect_surface_message(
>> + p, sfid, brw_writemask(brw_null_reg(), mask),
>> + payload, surface, msg_length, 0, align1);
>> +
>> + brw_set_dp_untyped_surface_write_message(
>> + p, insn, num_channels);
>> +}
>> +
>> void
>> brw_pixel_interpolator_query(struct brw_compile *p,
>> struct brw_reg dest,
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
>> b/src/mesa/drivers/dri/i965/brw_fs.cpp
>> index 6e6ce58..6d363f1 100644
>> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
>> @@ -508,6 +508,7 @@ fs_inst::is_send_from_grf() const
>> case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
>> case SHADER_OPCODE_UNTYPED_ATOMIC:
>> case SHADER_OPCODE_UNTYPED_SURFACE_READ:
>> + case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
>> case SHADER_OPCODE_URB_WRITE_SIMD8:
>> return true;
>> case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
>> @@ -930,6 +931,8 @@ fs_inst::regs_read(int arg) const
>> return mlen;
>> } else if (opcode == SHADER_OPCODE_UNTYPED_SURFACE_READ && arg == 0) {
>> return mlen;
>> + } else if (opcode == SHADER_OPCODE_UNTYPED_SURFACE_WRITE && arg == 0) {
>> + return mlen;
>> } else if (opcode == FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET && arg ==
>> 0) {
>> return mlen;
>> }
>> @@ -1020,6 +1023,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
>> return 2;
>> case SHADER_OPCODE_UNTYPED_ATOMIC:
>> case SHADER_OPCODE_UNTYPED_SURFACE_READ:
>> + case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
>> case SHADER_OPCODE_URB_WRITE_SIMD8:
>> case FS_OPCODE_INTERPOLATE_AT_CENTROID:
>> case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
>> b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
>> index a0aa64e..6e093cf 100644
>> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
>> @@ -1899,6 +1899,12 @@ fs_generator::generate_code(const cfg_t *cfg, int
>> dispatch_width)
>> brw_mark_surface_used(prog_data, src[1].dw1.ud);
>> break;
>>
>> + case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
>> + assert(src[2].file == BRW_IMMEDIATE_VALUE);
>> + brw_untyped_surface_write(p, src[0], src[1],
>> + inst->mlen, src[2].dw1.ud);
>> + break;
>> +
>> case SHADER_OPCODE_FIND_LIVE_CHANNEL:
>> brw_find_live_channel(p, dst);
>> break;
>> diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
>> b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
>> index 56f69ea..46b635c 100644
>> --- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
>> @@ -358,6 +358,7 @@ schedule_node::set_latency_gen7(bool is_haswell)
>> break;
>>
>> case SHADER_OPCODE_UNTYPED_SURFACE_READ:
>> + case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
>> /* Test code:
>> * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q
>> };
>> * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
>> diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
>> b/src/mesa/drivers/dri/i965/brw_shader.cpp
>> index dc4952e..b58796d 100644
>> --- a/src/mesa/drivers/dri/i965/brw_shader.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
>> @@ -458,6 +458,8 @@ brw_instruction_name(enum opcode op)
>> return "untyped_atomic";
>> case SHADER_OPCODE_UNTYPED_SURFACE_READ:
>> return "untyped_surface_read";
>> + case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
>> + return "untyped_surface_write";
>>
>> case SHADER_OPCODE_LOAD_PAYLOAD:
>> return "load_payload";
>> @@ -966,6 +968,7 @@ backend_instruction::has_side_effects() const
>> {
>> switch (opcode) {
>> case SHADER_OPCODE_UNTYPED_ATOMIC:
>> + case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
>> case SHADER_OPCODE_URB_WRITE_SIMD8:
>> case FS_OPCODE_FB_WRITE:
>> return true;
>> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
>> b/src/mesa/drivers/dri/i965/brw_vec4.cpp
>> index 0004b10..736437f 100644
>> --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
>> @@ -258,6 +258,7 @@ vec4_instruction::is_send_from_grf()
>> case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
>> case SHADER_OPCODE_UNTYPED_ATOMIC:
>> case SHADER_OPCODE_UNTYPED_SURFACE_READ:
>> + case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
>> return true;
>> default:
>> return false;
>> @@ -274,6 +275,7 @@ vec4_instruction::regs_read(unsigned arg) const
>> case SHADER_OPCODE_SHADER_TIME_ADD:
>> case SHADER_OPCODE_UNTYPED_ATOMIC:
>> case SHADER_OPCODE_UNTYPED_SURFACE_READ:
>> + case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
>> return arg == 0 ? mlen : 1;
>>
>> case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
>> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
>> b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
>> index 5c350fe..4c75b95 100644
>> --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
>> @@ -1474,6 +1474,12 @@ vec4_generator::generate_code(const cfg_t *cfg)
>> brw_mark_surface_used(&prog_data->base, src[1].dw1.ud);
>> break;
>>
>> + case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
>> + assert(src[2].file == BRW_IMMEDIATE_VALUE);
>> + brw_untyped_surface_write(p, src[0], src[1], inst->mlen,
>> + src[2].dw1.ud);
>> + break;
>> +
>> case SHADER_OPCODE_FIND_LIVE_CHANNEL:
>> brw_find_live_channel(p, dst);
>> break;
>> --
>> 2.1.3
>>
>> _______________________________________________
>> mesa-dev mailing list
>> mesa-dev@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
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