Overall this looks correct. I've got a few nits below and I'd like to take
a look at it with fresh eyes before giving an R-B as it's complicated
especially with all of the stuff to handle non-ssa. Not sure if it's
really worth doing non-ssa now that I see how much more complicated it
makes things.
--Jason
On Wed, Jan 21, 2015 at 5:26 PM, Eric Anholt <e...@anholt.net> wrote:
> This is the equivalent of brw_fs_channel_expressions.cpp, which I wanted
> for vc4.
> ---
>
> This series, plus a commit to make i965 use it instead of
> channel_expressions,
> is on the nir-scalarize branch of my mesa tree. With the whole series,
> there
> are 6 regressions, 3 of which are due to lower-vec-to-movs being broken
> when
> faced with "r0 = vec4 r0.yxxx, r0.xxxx, r0.zxxx, r0.wxxx" (fs-swap-problem
> test, for example). The other 3 are sampler-nonconst-2d-array and friends,
> which I haven't figured out yet.
>
> Full disclosure: I did a cleanup to use nir_alu_ssa_dest_init() more and
> haven't repiglited since then.
>
> The full i965 conversion has the following shader-db results for me,
> presumably because of losing GLSL-IR-level optimizations due to not
> splitting
> expressions in GLSL IR:
>
> total instructions in shared programs: 137974 -> 139306 (0.97%)
> instructions in affected programs: 55959 -> 57291 (2.38%)
>
> src/glsl/Makefile.sources | 1 +
> src/glsl/nir/nir.h | 1 +
> src/glsl/nir/nir_lower_alu_scalar.c | 287
> ++++++++++++++++++++++++++++++++++++
> 3 files changed, 289 insertions(+)
> create mode 100644 src/glsl/nir/nir_lower_alu_scalar.c
>
> diff --git a/src/glsl/Makefile.sources b/src/glsl/Makefile.sources
> index 6237627..9cd1a6a 100644
> --- a/src/glsl/Makefile.sources
> +++ b/src/glsl/Makefile.sources
> @@ -24,6 +24,7 @@ NIR_FILES = \
> $(GLSL_SRCDIR)/nir/nir_intrinsics.c \
> $(GLSL_SRCDIR)/nir/nir_intrinsics.h \
> $(GLSL_SRCDIR)/nir/nir_live_variables.c \
> + $(GLSL_SRCDIR)/nir/nir_lower_alu_scalar.c \
> $(GLSL_SRCDIR)/nir/nir_lower_atomics.c \
> $(GLSL_SRCDIR)/nir/nir_lower_global_vars_to_local.c \
> $(GLSL_SRCDIR)/nir/nir_lower_locals_to_regs.c \
> diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
> index 7f0aa36..fb42d91 100644
> --- a/src/glsl/nir/nir.h
> +++ b/src/glsl/nir/nir.h
> @@ -1521,6 +1521,7 @@ void nir_lower_vars_to_ssa(nir_shader *shader);
> void nir_remove_dead_variables(nir_shader *shader);
>
> void nir_lower_vec_to_movs(nir_shader *shader);
> +void nir_lower_ops_scalar(nir_shader *shader);
>
> void nir_lower_samplers(nir_shader *shader,
> struct gl_shader_program *shader_program,
> diff --git a/src/glsl/nir/nir_lower_alu_scalar.c
> b/src/glsl/nir/nir_lower_alu_scalar.c
> new file mode 100644
> index 0000000..e13ad1e
> --- /dev/null
> +++ b/src/glsl/nir/nir_lower_alu_scalar.c
> @@ -0,0 +1,287 @@
> +/*
> + * Copyright © 2014-2015 Broadcom
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without
> limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the
> next
> + * paragraph) shall be included in all copies or substantial portions of
> the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
> SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "nir.h"
> +
> +/** @file nir_lower_alu_scalar.c
> + *
> + * Replaces nir_alu_instr operations with more than one channel used in
> the
> + * arguments with individual per-channel operations.
> + */
> +
> +static void
> +unsupported(nir_instr *instr)
> +{
> + fprintf(stderr, "Unsupported instruction in scalar lowering: ");
> + nir_print_instr(instr, stderr);
> + fprintf(stderr, "\n");
> + abort();
> +}
> +
> +static void
> +nir_alu_ssa_dest_init(nir_alu_instr *instr, unsigned num_components)
> +{
> + nir_ssa_dest_init(&instr->instr, &instr->dest.dest, num_components,
> NULL);
> + instr->dest.write_mask = (1 << num_components) - 1;
> +}
> +
> +static void
> +reduce_op_replace(nir_alu_instr *instr, nir_ssa_def *def, void *mem_ctx)
> +{
> + assert(instr->dest.write_mask == 1);
> +
> + if (instr->dest.dest.is_ssa) {
> + nir_src new_src;
> + new_src.is_ssa = true;
> + new_src.ssa = def;
> + nir_ssa_def_rewrite_uses(&instr->dest.dest.ssa, new_src, mem_ctx);
> + } else {
> + nir_alu_instr *mov = nir_alu_instr_create(mem_ctx, nir_op_imov);
> + mov->src[0].src.is_ssa = true;
> + mov->src[0].src.ssa = def;
> +
> + nir_alu_dest_copy(&mov->dest, &instr->dest, mem_ctx);
> + nir_instr_insert_after(&instr->instr, &mov->instr);
I usually do insert_before when possible. It will result in the same list
(since we remove the instruction we're putting this before) but, since this
happens as we're iterating over it, insert_before is a bit safer. Maybe
this is still safe; I'm not sure.
> + }
> +
> + nir_instr_remove(&instr->instr);
> +}
> +
> +static void
> +lower_reduction(nir_alu_instr *instr, nir_op chan_op, nir_op merge_op,
> + void *mem_ctx)
> +{
> + unsigned num_components = nir_op_infos[instr->op].input_sizes[0];
> +
> + nir_ssa_def *last = NULL;
> + for (unsigned i = 0; i < num_components; i++) {
> + nir_alu_instr *chan = nir_alu_instr_create(mem_ctx, chan_op);
> + nir_alu_ssa_dest_init(chan, 1);
> + nir_alu_src_copy(&chan->src[0], &instr->src[0], mem_ctx);
> + chan->src[0].swizzle[0] = chan->src[0].swizzle[i];
> + if (nir_op_infos[chan_op].num_inputs > 1) {
>
assert num_inputs == 2 here?
> + nir_alu_src_copy(&chan->src[1], &instr->src[1], mem_ctx);
> + chan->src[1].swizzle[0] = chan->src[1].swizzle[i];
> + }
> +
> + nir_instr_insert_before(&instr->instr, &chan->instr);
> +
> + if (i == 0) {
> + last = &chan->dest.dest.ssa;
> + } else {
> + nir_alu_instr *merge = nir_alu_instr_create(mem_ctx, merge_op);
> + nir_alu_ssa_dest_init(merge, 1);
> + merge->dest.write_mask = 1;
> + merge->src[0].src.is_ssa = true;
> + merge->src[0].src.ssa = last;
> + merge->src[1].src.is_ssa = true;
> + merge->src[1].src.ssa = &chan->dest.dest.ssa;
> + nir_instr_insert_before(&instr->instr, &merge->instr);
> + last = &merge->dest.dest.ssa;
>
It might be nice if the tree were better balanced but that looks like way
too much work, so meh.
> + }
> + }
> +
> + reduce_op_replace(instr, last, mem_ctx);
> +}
> +
> +static void
> +lower_alu_instr_scalar(nir_function_impl *impl, nir_alu_instr *instr,
> + void *mem_ctx)
> +{
> + unsigned unmodified_chan; /* original instr will still write this
> channel */
> + if (instr->dest.dest.is_ssa)
> + unmodified_chan = 0;
> + else
> + unmodified_chan = 1 << (ffs(instr->dest.write_mask) - 1);
> + unsigned lower_chans = instr->dest.write_mask & ~unmodified_chan;
> + unsigned num_src = nir_op_infos[instr->op].num_inputs;
> + nir_alu_src src[num_src][4];
> + unsigned i, chan;
> +
> + assert(instr->dest.write_mask != 0);
> +
> +#define LOWER_REDUCTION(name, chan, merge) \
> + case name##2: \
> + case name##3: \
> + case name##4: \
> + lower_reduction(instr, chan, merge, mem_ctx); \
> + break;
> +
> + switch (instr->op) {
> + case nir_op_vec4:
> + case nir_op_vec3:
> + case nir_op_vec2:
> + /* We don't need to scalarize these ops, they're the ones generated
> to
> + * group up outputs into a value that can be SSAed.
> + */
> + return;
> +
> + LOWER_REDUCTION(nir_op_fdot, nir_op_fmul, nir_op_fadd);
> + LOWER_REDUCTION(nir_op_ball_fequal, nir_op_feq, nir_op_iand);
> + LOWER_REDUCTION(nir_op_ball_iequal, nir_op_ieq, nir_op_iand);
> + LOWER_REDUCTION(nir_op_bany_fnequal, nir_op_fne, nir_op_ior);
> + LOWER_REDUCTION(nir_op_bany_inequal, nir_op_ine, nir_op_ior);
> + LOWER_REDUCTION(nir_op_fall_equal, nir_op_seq, nir_op_fand);
> + LOWER_REDUCTION(nir_op_fany_nequal, nir_op_sne, nir_op_for);
> + LOWER_REDUCTION(nir_op_ball, nir_op_imov, nir_op_iand);
> + LOWER_REDUCTION(nir_op_bany, nir_op_imov, nir_op_ior);
> + LOWER_REDUCTION(nir_op_fall, nir_op_fmov, nir_op_fand);
> + LOWER_REDUCTION(nir_op_fany, nir_op_fmov, nir_op_for);
> +
> + default:
> + break;
> + }
> +
> + if (lower_chans == 0 || (instr->dest.dest.is_ssa &&
> + instr->dest.dest.ssa.num_components == 1)) {
> + return;
> + }
> +
> + for (i = 0; i < num_src; i++) {
> + bool aliased = (!instr->dest.dest.is_ssa &&
> + !instr->src[i].src.is_ssa &&
> + instr->src[i].src.reg.reg ==
> instr->dest.dest.reg.reg);
> +
> + for (unsigned chan = 0; chan < 4; chan++) {
> +
> + src[i][chan] = instr->src[i];
> + src[i][chan].swizzle[0] = instr->src[i].swizzle[chan];
> +
> + /* Unalias src registers from the destination. */
> + if (aliased) {
> + nir_alu_instr *mov = nir_alu_instr_create(mem_ctx,
> nir_op_imov);
> + mov->src[0] = src[i][chan];
> + mov->src[0].abs = false;
> + mov->src[0].negate = false;
> + nir_alu_ssa_dest_init(mov, 1);
> +
> + nir_instr_insert_before(&instr->instr, &mov->instr);
> +
> + src[i][chan].src.is_ssa = true;
> + src[i][chan].src.ssa = &mov->dest.dest.ssa;
> + src[i][chan].swizzle[0] = 0;
> + }
> + }
> + }
> +
> + nir_alu_instr *vec_instr = NULL;
> + if (instr->dest.dest.is_ssa) {
> + unsigned num_components = instr->dest.dest.ssa.num_components;
> + static const nir_op nir_op_map[] = {nir_op_vec2, nir_op_vec3,
> nir_op_vec4};
>
*sigh* Why have I been using switch statements this whole time? This is
soo much nicer than what I've been doing. Good work!
> + if (num_components < 2)
> + unsupported(&instr->instr);
> + vec_instr = nir_alu_instr_create(mem_ctx, nir_op_map[num_components
> - 2]);
> + nir_alu_ssa_dest_init(vec_instr, num_components);
> + }
> +
> + /* Walk from the end of the channels, so our incremental inserts after
> the
> + * original instruction end up in a sensible xyzw order.
> + */
> + for (chan = 0; chan < 4; chan++) {
> + if (!(lower_chans & (1 << chan))) {
> + if (instr->dest.dest.is_ssa &&
> + chan < instr->dest.dest.ssa.num_components) {
> + unsupported(&instr->instr);
> + }
> + continue;
> + }
> +
> + nir_alu_instr *lower = nir_alu_instr_create(mem_ctx, instr->op);
> + for (i = 0; i < num_src; i++) {
> + /* bcsel and fcsel reuse the same src channel in src[0]. */
>
Stale comment. This isn't the case for bcsel or fcsel anymore
> + unsigned src_chan = (nir_op_infos[instr->op].input_sizes[i] == 1
> ?
> + 0 : chan);
>
I think you want input_sizes[i] != 0 here. We could have an instruction
that takes a vec2 as one component but is otherwise vectorized.
> +
> + lower->src[i].src = nir_src_copy(src[i][src_chan].src, mem_ctx);
> + for (int j = 0; j < 4; j++)
> + lower->src[i].swizzle[j] = src[i][src_chan].swizzle[0];
> + lower->src[i].abs = src[i][src_chan].abs;
> + lower->src[i].negate = src[i][src_chan].negate;
> + }
> +
> + if (instr->dest.dest.is_ssa) {
> + nir_alu_ssa_dest_init(lower, 1);
> + vec_instr->src[chan].src.is_ssa = true;
> + vec_instr->src[chan].src.ssa = &lower->dest.dest.ssa;
> + } else {
> + lower->dest.dest.reg.reg = instr->dest.dest.reg.reg;
> + lower->dest.write_mask = 1 << chan;
> + }
> + lower->dest.saturate = instr->dest.saturate;
> +
> + nir_instr_insert_before(&instr->instr, &lower->instr);
> + }
> +
> + if (instr->dest.dest.is_ssa) {
> + nir_instr_insert_after(&instr->instr, &vec_instr->instr);
> +
> + nir_src new_src;
> + new_src.is_ssa = true;
> + new_src.ssa = &vec_instr->dest.dest.ssa;
> + nir_ssa_def_rewrite_uses(&instr->dest.dest.ssa, new_src, mem_ctx);
> +
> + nir_instr_remove(&instr->instr);
> + } else {
> + instr->dest.write_mask = unmodified_chan;
> + }
> +}
> +
> +struct lower_context {
> + void *mem_ctx;
> + nir_function_impl *impl;
> +};
> +
> +static bool
> +lower_ops_scalar_block(nir_block *block, void *data)
> +{
> + struct lower_context *lower_context = data;
> +
> + nir_foreach_instr_safe(block, instr) {
> + if (instr->type == nir_instr_type_alu)
> + lower_alu_instr_scalar(lower_context->impl,
> + (nir_alu_instr *)instr,
> + lower_context->mem_ctx);
> + }
> +
> + return true;
> +}
> +
> +static void
> +nir_lower_ops_scalar_impl(nir_function_impl *impl)
> +{
> + struct lower_context lower_context;
> +
> + lower_context.mem_ctx = ralloc_parent(impl);
> + lower_context.impl = impl;
> +
> + nir_foreach_block(impl, lower_ops_scalar_block, &lower_context);
> +}
> +
> +void
> +nir_lower_ops_scalar(nir_shader *shader)
> +{
> + nir_foreach_overload(shader, overload) {
> + if (overload->impl)
> + nir_lower_ops_scalar_impl(overload->impl);
> + }
> +}
> --
> 2.1.3
>
> _______________________________________________
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