Signed-off-by: Connor Abbott <connor.abb...@intel.com>
---
src/mesa/drivers/dri/i965/brw_fs.h | 5 +++--
src/mesa/drivers/dri/i965/brw_fs_fp.cpp | 5 +++--
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 30 +++++++++++++++++-----------
3 files changed, 24 insertions(+), 16 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 9ba3f38..f62c6a1 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -376,10 +376,11 @@ public:
fs_reg shadow_comp, fs_reg lod, fs_reg lod2);
fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
- fs_reg sample_index);
+ fs_reg sample_index, bool has_offset);
fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
- fs_reg sample_index, fs_reg mcs, int sampler);
+ fs_reg sample_index, bool has_offset,
+ fs_reg offset, fs_reg mcs, int sampler);
fs_reg emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, int sampler);
void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
fs_reg fix_math_operand(fs_reg src);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
index 80075dd6..e5d29ae 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
@@ -406,6 +406,7 @@ fs_visitor::emit_fragment_program_code()
fs_reg coordinate = src[0];
fs_reg shadow_c;
fs_reg sample_index;
+ fs_reg offset;
switch (fpi->Opcode) {
case OPCODE_TEX:
@@ -489,9 +490,9 @@ fs_visitor::emit_fragment_program_code()
fs_inst *inst;
if (brw->gen >= 7) {
- inst = emit_texture_gen7(ir, dst, coordinate, shadow_c, lod, dpdy,
sample_index, fs_reg(0u), fpi->TexSrcUnit);
+ inst = emit_texture_gen7(ir, dst, coordinate, shadow_c, lod, dpdy,
sample_index, false, offset, fs_reg(0u), fpi->TexSrcUnit);
} else if (brw->gen >= 5) {
- inst = emit_texture_gen5(ir, dst, coordinate, shadow_c, lod, dpdy,
sample_index);
+ inst = emit_texture_gen5(ir, dst, coordinate, shadow_c, lod, dpdy,
sample_index, false);
} else {
inst = emit_texture_gen4(ir, dst, coordinate, shadow_c, lod, dpdy);
}
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 18cfb76..6e54e70 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1277,7 +1277,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst,
fs_reg coordinate,
fs_inst *
fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
fs_reg shadow_c, fs_reg lod, fs_reg lod2,
- fs_reg sample_index)
+ fs_reg sample_index, bool has_offset)
{
int mlen = 0;
int base_mrf = 2;
@@ -1286,7 +1286,7 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst,
fs_reg coordinate,
const int vector_elements =
ir->coordinate ? ir->coordinate->type->vector_elements : 0;
- if (ir->offset) {
+ if (has_offset) {
/* The offsets set up by the ir_texture visitor are in the
* m1 header, so we can't go headerless.
*/
@@ -1404,7 +1404,8 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst,
fs_reg coordinate,
fs_inst *
fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
fs_reg shadow_c, fs_reg lod, fs_reg lod2,
- fs_reg sample_index, fs_reg mcs, int sampler)
+ fs_reg sample_index, bool has_offset,
+ fs_reg offset, fs_reg mcs, int sampler)
{
int reg_width = dispatch_width / 8;
bool header_present = false;
@@ -1415,7 +1416,7 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst,
fs_reg coordinate,
}
int length = 0;
- if (ir->op == ir_tg4 || (ir->offset && ir->op != ir_txf) || sampler >= 16) {
+ if (ir->op == ir_tg4 || (has_offset && ir->op != ir_txf) || sampler >= 16) {
/* For general texture offsets (no txf workaround), we need a header to
* put them in. Note that for SIMD16 we're making space for two actual
* hardware registers here, so the emit will have to fix up for this.
@@ -1436,7 +1437,7 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst,
fs_reg coordinate,
length++;
}
- bool has_nonconstant_offset = ir->offset && !ir->offset->as_constant();
+ bool has_nonconstant_offset = has_offset && offset.file != BAD_FILE;
bool coordinate_done = false;
/* Set up the LOD info */
@@ -1530,9 +1531,6 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst,
fs_reg coordinate,
no16("Gen7 does not support gather4_po_c in SIMD16 mode.");
/* More crazy intermixing */
- ir->offset->accept(this);
- fs_reg offset_value = this->result;
-
for (int i = 0; i < 2; i++) { /* u, v */
emit(MOV(sources[length], coordinate));
coordinate.reg_offset++;
@@ -1540,8 +1538,8 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst,
fs_reg coordinate,
}
for (int i = 0; i < 2; i++) { /* offu, offv */
- emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D),
offset_value));
- offset_value.reg_offset++;
+ emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), offset));
+ offset.reg_offset++;
length++;
}
@@ -1853,12 +1851,20 @@ fs_visitor::visit(ir_texture *ir)
*/
fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4,
1));
+ bool has_offset = ir->offset != NULL;
+ fs_reg offset;
+ if (has_offset && ir->offset->as_constant()) {
+ ir->offset->accept(this);
+ offset = this->result;
+ }
+
if (brw->gen >= 7) {
inst = emit_texture_gen7(ir, dst, coordinate, shadow_comparitor,
- lod, lod2, sample_index, mcs, sampler);
+ lod, lod2, sample_index, has_offset, offset,
+ mcs, sampler);
} else if (brw->gen >= 5) {
inst = emit_texture_gen5(ir, dst, coordinate, shadow_comparitor,
- lod, lod2, sample_index);
+ lod, lod2, sample_index, has_offset);
} else {
inst = emit_texture_gen4(ir, dst, coordinate, shadow_comparitor,
lod, lod2);
--
1.9.3
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