Change from "not cacheable" to "cacheable" in L3.
Do so for the draw upload path and blorp.
CC: Kenneth Graunke <kenn...@whitecape.org>
Signed-off-by: Chad Versace <chad.vers...@linux.intel.com>
---
src/mesa/drivers/dri/i965/brw_draw_upload.c | 3 +++
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 3 +++
2 files changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 2952027..897e733 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -658,6 +658,9 @@ static void brw_emit_vertices(struct brw_context *brw)
if (brw->gen >= 7)
dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
+ if (brw->is_haswell)
+ dw0 |= GEN7_MOCS_L3 << 16;
+
OUT_BATCH(dw0 | (buffer->stride << BRW_VB0_PITCH_SHIFT));
OUT_RELOC(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->offset);
if (brw->gen >= 5) {
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index fd220f6..904568c 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -170,6 +170,9 @@ gen6_blorp_emit_vertices(struct brw_context *brw,
if (brw->gen >= 7)
dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
+ if (brw->is_haswell)
+ dw0 |= GEN7_MOCS_L3 << 16;
+
BEGIN_BATCH(batch_length);
OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2));
OUT_BATCH(dw0);
--
1.8.3.1
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