Change from "not cacheable" to "cacheable" in L3.
Do so for the draw upload path and blorp.
CC: Kenneth Graunke <kenn...@whitecape.org>
Signed-off-by: Chad Versace <chad.vers...@linux.intel.com>
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 9 ++++++++-
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 9 ++++++++-
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 0ab1e76..cfd5acf 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -1023,13 +1023,20 @@ static void upload_state_base_address( struct
brw_context *brw )
*/
if (brw->gen >= 6) {
+ /* The MOCS of the STATE_BASE_ADDRESS applies to stateless buffers
+ * accessed by the data port, indirect state objects, and shader kernels.
+ * See the PRM, Section "Memory Object Control State".
+ */
+ uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
+
if (brw->gen == 6)
intel_emit_post_sync_nonzero_flush(brw);
BEGIN_BATCH(10);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
/* General state base address: stateless DP read/write requests */
- OUT_BATCH(1);
+ OUT_BATCH(mocs << 8 |
+ 1 /*GeneralStateBaseAddressModifyEnable*/);
/* Surface state base address:
* BINDING_TABLE_STATE
* SURFACE_STATE
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 8056bf5..fd220f6 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -74,9 +74,16 @@ void
gen6_blorp_emit_state_base_address(struct brw_context *brw,
const brw_blorp_params *params)
{
+ /* The MOCS of the STATE_BASE_ADDRESS applies to stateless buffers accessed
+ * by the data port, indirect state objects, and shader kernels. See the
+ * PRM, Section "Memory Object Control State".
+ */
+ uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
+
BEGIN_BATCH(10);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
- OUT_BATCH(1); /* GeneralStateBaseAddressModifyEnable */
+ OUT_BATCH(mocs << 8 |
+ 1 /* GeneralStateBaseAddressModifyEnable */);
/* SurfaceStateBaseAddress */
OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
/* DynamicStateBaseAddress */
--
1.8.3.1
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