On Thu, Oct 4, 2018 at 3:25 AM Samuel Pitoiset
<samuel.pitoi...@gmail.com> wrote:
>
>
>
> On 10/3/18 12:35 AM, Marek Olšák wrote:
> > From: Marek Olšák <marek.ol...@amd.com>
> >
> > ---
> > src/amd/common/sid.h | 5 +++++
> > src/gallium/drivers/radeonsi/si_fence.c | 19 ++++++++++---------
> > src/gallium/drivers/radeonsi/si_perfcounter.c | 2 ++
> > src/gallium/drivers/radeonsi/si_pipe.h | 2 +-
> > src/gallium/drivers/radeonsi/si_query.c | 9 +++++++--
> > src/gallium/drivers/radeonsi/si_state_draw.c | 8 ++++++--
> > 6 files changed, 31 insertions(+), 14 deletions(-)
> >
> > diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
> > index b3321ea3a77..3e36eb2d046 100644
> > --- a/src/amd/common/sid.h
> > +++ b/src/amd/common/sid.h
> > @@ -174,28 +174,33 @@
> > #define COPY_DATA_DST_MEM 5
> > #define COPY_DATA_COUNT_SEL (1 << 16)
> > #define COPY_DATA_WR_CONFIRM (1 << 20)
> > #define COPY_DATA_ENGINE_PFP (1 << 30)
> > #define PKT3_PFP_SYNC_ME 0x42
> > #define PKT3_SURFACE_SYNC 0x43 /* deprecated on CIK,
> > use ACQUIRE_MEM */
> > #define PKT3_ME_INITIALIZE 0x44 /* not on CIK */
> > #define PKT3_COND_WRITE 0x45
> > #define PKT3_EVENT_WRITE 0x46
> > #define PKT3_EVENT_WRITE_EOP 0x47 /* not on GFX9 */
> > +#define EOP_DST_SEL(x) ((x) << 16)
> > +#define EOP_DST_SEL_MEM 0
> > +#define EOP_DST_SEL_TC_L2 1
> > #define EOP_INT_SEL(x) ((x) << 24)
> > #define EOP_INT_SEL_NONE 0
> > #define EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM 3
> > #define EOP_DATA_SEL(x) ((x) << 29)
> > #define EOP_DATA_SEL_DISCARD 0
> > #define EOP_DATA_SEL_VALUE_32BIT 1
> > #define EOP_DATA_SEL_VALUE_64BIT 2
> > #define EOP_DATA_SEL_TIMESTAMP 3
> > +#define EOP_DATA_SEL_GDS 5
> > +#define EOP_DATA_GDS(dw_offset, num_dwords) ((dw_offset)
> > | ((unsigned)(num_dwords) << 16))
> > /* CP DMA bug: Any use of CP_DMA.DST_SEL=TC must be avoided when EOS
> > packets
> > * are used. Use DST_SEL=MC instead. For prefetch, use SRC_SEL=TC and
> > * DST_SEL=MC. Only CIK chips are affected.
> > */
> > /* fix CP DMA before uncommenting: */
> > /*#define PKT3_EVENT_WRITE_EOS 0x48*/ /* not on GFX9 */
> > #define PKT3_RELEASE_MEM 0x49 /* GFX9+ [any ring]
> > or GFX8 [compute ring only] */
> > #define PKT3_ONE_REG_WRITE 0x57 /* not on CIK */
> > #define PKT3_ACQUIRE_MEM 0x58 /* new for CIK */
> > #define PKT3_SET_CONFIG_REG 0x68
> > diff --git a/src/gallium/drivers/radeonsi/si_fence.c
> > b/src/gallium/drivers/radeonsi/si_fence.c
> > index abb7057f299..005fd9c1576 100644
> > --- a/src/gallium/drivers/radeonsi/si_fence.c
> > +++ b/src/gallium/drivers/radeonsi/si_fence.c
> > @@ -59,34 +59,32 @@ struct si_multi_fence {
> > * \param event EVENT_TYPE_*
> > * \param event_flags Optional cache flush flags (TC)
> > * \param data_sel 1 = fence, 3 = timestamp
> > * \param buf Buffer
> > * \param va GPU address
> > * \param old_value Previous fence value (for a bug workaround)
> > * \param new_value Fence value to write for this event.
> > */
>
> You might want to update the documentation too.
Done locally.
Marek
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