From: Marek Olšák <marek.ol...@amd.com>
---
src/amd/common/ac_gpu_info.c | 13 +++++++++++--
src/amd/common/ac_gpu_info.h | 3 ++-
src/amd/vulkan/si_cmd_buffer.c | 2 +-
src/gallium/drivers/radeonsi/si_pipe.c | 9 +++++++++
src/gallium/drivers/radeonsi/si_pipe.h | 3 +++
src/gallium/drivers/radeonsi/si_state.c | 12 +++++-------
6 files changed, 31 insertions(+), 11 deletions(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 766ad835476..d6df2f6443e 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -636,23 +636,24 @@ ac_get_gs_table_depth(enum chip_class chip_class, enum
radeon_family family)
case CHIP_VEGAM:
return 32;
default:
unreachable("Unknown GPU");
}
}
void
ac_get_raster_config(struct radeon_info *info,
uint32_t *raster_config_p,
- uint32_t *raster_config_1_p)
+ uint32_t *raster_config_1_p,
+ uint32_t *se_tile_repeat_p)
{
- unsigned raster_config, raster_config_1;
+ unsigned raster_config, raster_config_1, se_tile_repeat;
switch (info->family) {
/* 1 SE / 1 RB */
case CHIP_HAINAN:
case CHIP_KABINI:
case CHIP_MULLINS:
case CHIP_STONEY:
raster_config = 0x00000000;
raster_config_1 = 0x00000000;
break;
@@ -715,22 +716,30 @@ ac_get_raster_config(struct radeon_info *info,
/* Fiji: Old kernels have incorrect tiling config. This decreases
* RB performance by 25%. (it disables 1 RB in the second packer)
*/
if (info->family == CHIP_FIJI &&
info->cik_macrotile_mode_array[0] == 0x000000e8) {
raster_config = 0x16000012;
raster_config_1 = 0x0000002a;
}
+ unsigned se_width = 8 << G_028350_SE_XSEL_GFX6(raster_config);
+ unsigned se_height = 8 << G_028350_SE_YSEL_GFX6(raster_config);
+
+ /* I don't know how to calculate this, though this is probably a good
guess. */
+ se_tile_repeat = MAX2(se_width, se_height) * info->max_se;
+
*raster_config_p = raster_config;
*raster_config_1_p = raster_config_1;
+ if (se_tile_repeat_p)
+ *se_tile_repeat_p = se_tile_repeat;
}
void
ac_get_harvested_configs(struct radeon_info *info,
unsigned raster_config,
unsigned *cik_raster_config_1_p,
unsigned *raster_config_se)
{
unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
unsigned num_se = MAX2(info->max_se, 1);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 0583a6037f2..a7dc1094c05 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -143,21 +143,22 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
struct radeon_info *info,
struct amdgpu_gpu_info *amdinfo);
void ac_compute_driver_uuid(char *uuid, size_t size);
void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size);
void ac_print_gpu_info(struct radeon_info *info);
int ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family
family);
void ac_get_raster_config(struct radeon_info *info,
uint32_t *raster_config_p,
- uint32_t *raster_config_1_p);
+ uint32_t *raster_config_1_p,
+ uint32_t *se_tile_repeat_p);
void ac_get_harvested_configs(struct radeon_info *info,
unsigned raster_config,
unsigned *cik_raster_config_1_p,
unsigned *raster_config_se);
static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
{
switch (family) {
/* These always have 8 waves: */
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index e0d474756a3..de057657ee7 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -127,21 +127,21 @@ static unsigned radv_pack_float_12p4(float x)
static void
si_set_raster_config(struct radv_physical_device *physical_device,
struct radeon_cmdbuf *cs)
{
unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends,
16);
unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
unsigned raster_config, raster_config_1;
ac_get_raster_config(&physical_device->rad_info,
&raster_config,
- &raster_config_1);
+ &raster_config_1, NULL);
/* Always use the default config when all backends are enabled
* (or when we failed to determine the enabled backends).
*/
if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
raster_config);
if (physical_device->rad_info.chip_class >= CIK)
radeon_set_context_reg(cs,
R_028354_PA_SC_RASTER_CONFIG_1,
raster_config_1);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index c0b23ee5f6e..4da361c42ee 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -815,20 +815,29 @@ struct pipe_screen *radeonsi_screen_create(struct
radeon_winsys *ws,
unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i;
if (!sscreen) {
return NULL;
}
sscreen->ws = ws;
ws->query_info(ws, &sscreen->info);
si_handle_env_var_force_family(sscreen);
+ if (sscreen->info.chip_class >= GFX9) {
+ sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
+ } else {
+ ac_get_raster_config(&sscreen->info,
+ &sscreen->pa_sc_raster_config,
+ &sscreen->pa_sc_raster_config_1,
+ &sscreen->se_tile_repeat);
+ }
+
sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
debug_options, 0);
/* Set functions first. */
sscreen->b.context_create = si_pipe_create_context;
sscreen->b.destroy = si_destroy_screen;
si_init_screen_get_functions(sscreen);
si_init_screen_buffer_functions(sscreen);
si_init_screen_fence_functions(sscreen);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index dad3029bc31..ff11eab0224 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -398,20 +398,23 @@ struct radeon_saved_cs {
struct si_screen {
struct pipe_screen b;
struct radeon_winsys *ws;
struct disk_cache *disk_shader_cache;
struct radeon_info info;
uint64_t debug_flags;
char renderer_string[183];
+ unsigned pa_sc_raster_config;
+ unsigned pa_sc_raster_config_1;
+ unsigned se_tile_repeat;
unsigned gs_table_depth;
unsigned tess_offchip_block_dw_size;
unsigned tess_offchip_ring_size;
unsigned tess_factor_ring_size;
unsigned vgt_hs_offchip_param;
unsigned eqaa_force_coverage_samples;
unsigned eqaa_force_z_samples;
unsigned eqaa_force_color_samples;
bool has_clear_state;
bool has_distributed_tess;
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index aa57b3f0800..c2d3a6660ad 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -4803,27 +4803,25 @@ si_write_harvested_raster_configs(struct si_context
*sctx,
}
si_set_grbm_gfx_index(sctx, pm4, ~0);
if (sctx->chip_class >= CIK) {
si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
raster_config_1);
}
}
static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state
*pm4)
{
- unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16);
- unsigned rb_mask = sctx->screen->info.enabled_rb_mask;
- unsigned raster_config, raster_config_1;
-
- ac_get_raster_config(&sctx->screen->info,
- &raster_config,
- &raster_config_1);
+ struct si_screen *sscreen = sctx->screen;
+ unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16);
+ unsigned rb_mask = sscreen->info.enabled_rb_mask;
+ unsigned raster_config = sscreen->pa_sc_raster_config;
+ unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
/* Always use the default config when all backends are enabled
* (or when we failed to determine the enabled backends).
*/
si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
raster_config);
if (sctx->chip_class >= CIK)
si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
raster_config_1);
--
2.17.1
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