Timothy Arceri <tarc...@itsqueeze.com> writes: > This makes this opt behave more like the GLSL IR opt > lower_if_to_cond_assign(). With this we can disable that GLSL IR > opt on drivers with a NIR backend without causing spill > regressions. > > shader-db results for radeonsi (RX580): > > Totals from affected shaders: > SGPRS: 12200 -> 13072 (7.15 %) > VGPRS: 13496 -> 11840 (-12.27 %) > Spilled SGPRs: 285 -> 290 (1.75 %) > Spilled VGPRs: 115 -> 0 (-100.00 %) > Private memory VGPRs: 0 -> 0 (0.00 %) > Scratch size: 116 -> 0 (-100.00 %) dwords per thread > Code Size: 781304 -> 770168 (-1.43 %) bytes > LDS: 0 -> 0 (0.00 %) blocks > Max Waves: 1558 -> 1586 (1.80 %) > Wait states: 0 -> 0 (0.00 %)
Moving UBO loads out of conditionals seems questionable to me, and I don't think shader-db would represent the effect of this kind of code transformation well. I'd love to see some actual performance numbers on affected applications. That said, lower_if_to_cond_assign() was already doing this, and I'm assuming these shader-db stats are just from with-glsl-optimization-disabled to with-nir-patch. So, while we should probably investigate tuning this, since it lets us dump some GLSL optimization: Acked-by: Eric Anholt <e...@anholt.net>
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